A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0–500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 GΩ and a very low input resistance of 0.07 Ω.     

CMOS CCII– based on modified dual output-OTA for high frequency applications

A negative CMOS second generation current conveyor (CMOS CCII–) based on modified dual output CMOS folded cascode operational transconductance amplifier (CMOS DO-OTA) is presented. The proposed folded cascode CMOS DO-OTA with attractive features for high frequency operation such as high output impedance, wide bandwidth, high slew rate, with low power consumption is used in the realisation. The proposed CMOS DO-OTA and CMOS CCII– with high performance parameters can be used in many high frequency applications. The proposed CMOS CCII– achieves 1.37 GHz (?3 dB BW), 1.8 ns settling time, 48 V/μs slew rate, and low power consumption around 3.25 mW for ±2.5 V supply. P-Spice simulation results are included for 0.5 μm MIETEC CMOS technology.     

A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications

This paper describes a 0.8 V 700 μW CMOS low-voltage regulated cascode trans-impedance amplifier (TIA). It reduces the need for extra bias voltages compared to other recent low-voltage regulated cascode topologies. A trans-impedance gain of around 60 dBΩ along with a 40 GHz bandwidth was achieved using the 0.13 μm IBM CMOS process technology. The input referred noise current spectral density was below $ {{{18{\mathrm{pA}}}} \left/ {{\sqrt {\mathrm{Hz}} }} \right.} $ within the -3 dB noise bandwidth. Eye diagram simulations using a ?53dBm input photo-diode current signal and a 2³¹-1 pseudo random bit sequence data pattern, indicates an eye opening of 90 % at 10Gbit/s and 50 % at 40Gbit/s. This proposed RGC TIA is thus a robust building block for numerous optical sensing applications with low bit error ratio (BER) figure.     

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0–440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

一种集成低压低功耗电流复制电路设计

本文提出了一种集成低压低功耗电流复制电路。利用单级放大器和电压跟随器构成的负反馈回路实现对输入电压跟的跟随,利用等比例电阻实现电流的等比例复制,电路结构简单,仅由5个MOS管和2个等比例电阻构成。基于TSMC 0.18μm工艺完成电路设计,使Spectre完成电路仿真。结果表明,电路电源电压为1V时,电路静态功耗仅为1μW。在输入电流范围为0-50μA时,输出电流线性跟随输入电流,当输入电流大于3μA时,电流复制精度大于99%,电路带宽为31MHz。     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A high-gain complementary metal-oxide semiconductor op amp using composite cascode stages

In this work, a complementary metal-oxide semiconductor (CMOS) op amp design using composite cascode stages is reported. The design follows the classic Widlar architecture and is fabricated on a 0.25 μm CMOS process. The measured gain of 117 dB is comparable to that achieved in bipolar designs in this architecture. This design is suited for precision instrumentation applications where high gain, low input offset voltage and small cell size are important. It provides a common-mode input range of ?1 to 0.7 V using±1 V power supplies with a quiescent current of 55 μA. The use of the composite cascode also allows for dominant pole compensation with a single capacitor. A phase margin of 43° is achieved with a 3.5 pF compensation capacitor. The resulting cell size for the core op-amp circuit is approximately 24 × 16 mils, including large common centroid input devices that achieve an input offset voltage in the 1 mV range.     

Instrumentation amplifier and current injection circuit design for input impedance boosting in biopotential and bioimpedance measurements

This paper describes an instrumentation amplifier (IA) architecture with a mechanism that generates negative capacitances at its input. Two 8-bit programmable capacitors between the input stage and the current feedback loop of the IA allow adaptive cancellation of the input capacitances from the electrode cables and printed circuit board. The proposed negative capacitance generation technique can improve the input impedance from a few megaohms to above 500 MΩ without significant impact on performance parameters such as the common-mode rejection ratio, power supply rejection ratio, total harmonic distortion, and noise. Furthermore, a current injection circuit is introduced for on-chip input impedance estimation. An operational transconductance amplifier and associated key design concepts are presented in this paper that achieve a transconductance of 25 pS and an output impedance above 4 GΩ. The IA and the test current generator were designed and simulated using 0.13 µm CMOS technology.     

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-μm CMOS process model under supply voltage of ±0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Ω for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.     

Phase-margin enhancement technique for recycling folded cascode amplifier

A novel circuit technique for enhancing the phase-margin of the recycling folded cascode amplifier is presented. Compared to the conventional recycling folded cascade, using a high-speed current mirror, the proposed amplifier offers the advantage of cancellation of the first non-dominant pole, allowing the phase-margin to be enhanced without affecting the bandwidth. The proposed amplifier was implemented in CSMC standard 0.18 μm CMOS process. Simulation results show that the phase-margin enhancement of 20° is achieved without limiting the bandwidth.     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35μm CMOS

A 3.125-Gb/s transimpedance amplifier(TIA) for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point.In addition,noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩand -3 dB bandwidth of 2.31 GHz.The measured average input referred noise current spectral density is about 18.8 pA/(?).The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS.Under a single 3.3-V supply voltage,the TIA consumes only 58.08 mW,including 20 mW from the output buffer.The whole die area is 465×435μm~2.     

A high CMRR, class AB, fully differential current output stage

A true class ‘AB’ fully differential current output stage with very high common mode rejection ratio is presented in this study. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by SPICE simulation in TSMC 0.18 μm CMOS, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high common-mode rejection ratio (CMRR), high slew rate, high current drive capability, high output compliance, and very low power consumption while operating at power supply of ±0.9 V. The interesting results such as current drive capability of ±100 μA, high output voltage swing of ±0.8 V, low static power consumption of 21 μW, and very high CMRR of 84.5 dB is achieved utilizing standard CMOS technology. The performance of circuit at the presence of process and voltage variations evaluated through corner case and Monte Carlo analysis. The harmonic distortion is evaluated to investigate the circuit’s linearity. The transient stepwise response analysis is also done to verify the stability of proposed class ‘AB’ FDCOS.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.