Petri net modeling of gate and interconnect delays for power estimation

Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS '89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs

In this paper, we investigate the estimation of switching activity in VLSI circuits using a graphical probabilistic model based on cascaded Bayesian networks (CBNs). First, we develop a theoretical analysis for Bayesian inferencing of switching activity and then derive upper bounds for certain circuit parameters which, in turn, are useful in establishing the cascade structure of the CBN model. We formulate an elegant framework for maintaining probabilistic consistency in the interfacing boundaries across the CBNs during the inference process using a tree-dependent (TD) probability distribution function. A TD distribution is an approximation of the true joint probability function over the switching variables, with the constraint that the underlying BN representation is a tree. The tree approximation of the true joint probability function can be arrived at by using a maximum weight spanning tree (MWST) built using pairwise mutual information about the switching occurring at pairs of signal lines on the boundary. Further, we show that the proposed TD distribution function can be used to model correlations among the primary inputs which is critical for accuracy in modeling of switching activity. Experimental results for ISCAS circuits are presented to illustrate the efficacy of the proposed CBN models.     

Reliability evaluation of logic circuits using probabilistic gate models

Logic circuits built using nanoscale technologies have significant reliability limitations due to fundamental physical and manufacturing constraints of their constituent devices. This paper presents a probabilistic gate model (PGM), which relates the output probability to the error and input probabilities of an unreliable logic gate. The PGM is used to obtain computational algorithms, one being approximate and the other accurate, for the evaluation of circuit reliability. The complexity of the approximate algorithm, which does not consider dependencies among signals, increases linearly with the number of gates in a circuit. The accurate algorithm, which accounts for signal dependencies due to reconvergent fanouts and/or correlated inputs, has a worst-case complexity that is exponential in the numbers of dependent reconvergent fanouts and correlated inputs. By leveraging the fact that many large circuits consist of common logic modules, a modular approach that hierarchically decomposes a circuit into smaller modules and subsequently applies the accurate PGM algorithm to each module, is further proposed. Simulation results are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the modular PGM approach provides highly accurate results with a moderate computational complexity. It can further be embedded into an early design flow and is scalable for use in the reliability evaluation of large circuits.     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

The new possibilities of telephone switching

Switching system architectures have evolved to be responsive to the needs of the user. Their design has been constrained by the existing environment which treats terminals, transmission channels, and switching entities as separate "black boxes." Telephone switching circuits have used relatively expensive discrete components, and hence, system designers used common control techniques to minimize the system cost. This was done by providing the circuits in common whenever this was possible. Such common circuits were associated with a switched path for the period of time for which the functions of the circuit were required. This was followed by "one at a time" operation and by the use of stored program controls. The advent of low-cost electronic circuit components has resulted in the application of digital techniques to switching systems. For the first time, the combination of switching and transmission is possible. This is the near-term objective. The long-term objective, made possible by forecasts of low-cost memory and electronic gate circuits, is the combination of switching, transmission, and the terminals. This will result in much more complex terminals.     

基于概率表达式的MPRM电路功耗计算方法

采用基于信号概率的功耗计算模型进行MPRM（Mixed Polarity Reed-Muller）电路功耗优化,信号概率计算是功耗计算的关键.提出一种基于概率表达式的MPRM电路功耗计算方法.该方法兼顾信号概率计算的时间效率和准确性,对MPRM电路中不存在空间相关性的信号通过在电路中传播信号概率的方式计算其信号概率,存在空间相关性的信号则利用概率表达式计算其信号概率,并在电路中传播概率表达式以解决空间相关性问题,在此基础之上根据基于信号概率建立的解析动态功耗和静态功耗计算模型计算电路功耗.为进一步提高时间效率,该方法采用二元矩图表示概率表达式.使用基准电路对所提出方法进行了验证,并与其他采用不同信号概率计算方法的MPRM电路功耗计算方法进行了比较.结果表明所提出方法准确有效.     

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.     

A Low Power Pseudo-Random BIST Technique

Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.     

Ring oscillator circuit simulation with physical model for GaAs/GaAlAs heterojunction bipolar transistors

Switching performance is simulated for GaAs/GaAlAs heterojunction bipolar transistors (HBT's) by combining a realistic physical device model that involves numerical solutions for carrier transport equations and Poisson's equation with our own circuit simulator that enables direct access to the device model embedded in arbitrary circuits. Based on simulated results for five-stage ring oscillators, discussion is given as to how the switching performance depends on the circuit configuration such as current mode logic (CML) without and with emitter follower, and direct-coupled transistor logic (DCTL), inclusion or exclusion of external base areas, and choice for single-or double-heterojunction transistors.     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

Analysis of the conditions for the worst case switching activity in integrated circuits

Relentless advances in IC technologies have fueled steady increases on fabricated component density and working frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be triggered that compromise behavior. This can be either a consequence of a decrease in bias levels in the power grid caused by IR-Drop, or due to unexpected glitching on gates’ outputs caused by ground bounce. For proper circuit verification, both conditions have to be accurately estimated and accounted for. Achieving this in an accurate manner for a large circuit is a very challenging problem. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Our approach is based on both spatial and time partitioning which are used to address the accuracy and computational requirements. We propose a method for determining the exact conditions for worst case switching activity in a small circuit area during a short time interval. We then show how this method can be combined with partitioning to allow for accurate full circuit verification.     

Efficient statistical approach to estimate power consideringuncertain properties of primary inputs

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately     

基于伯努利分布的逻辑电路可靠度计算方法

在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.本文提出了一种利用概率统计模型计算逻辑电路可靠度的方法,将电路中的每个逻辑门是否正常输出看作一次随机事件,则发生故障的逻辑门数为某个特定值的概率服从伯努利分布;再利用实验统计单个逻辑门出错时电路的逻辑屏蔽特性,根据此方法计算出ISCAS'85和ISCAS'89基准电路可靠度的一个特定范围.理论分析和实验结果表明所提方法是准确和有效的.     

The Performance of Random and Optimal Scheduling in a Time-Multiplex Switch

In a time-multiplex switching system, the incoming traffic must be scheduled to avoid conflict at the switch output (two or more users converging simultaneously upon a single output). Two scheduling algorithms, random scheduling and optimal scheduling, are explored in this paper. Random scheduling is computationally simple, whereas optimal scheduling is currently very difficult. We have found, using a traffic model appropriate for circuit switched traffic that increases of typically 10 to 15 percent in offered load can be obtained through optimal scheduling (as compared to the much simpler random scheduling algorithm). The improvement is a function of the number of time slots (or circuits) per time-multiplexed frame, and falls to zero for both very small and very large frame sizes. Thus, in many circuit switching applications, providing a computationally expensive optimal schedule may not be warranted. This conclusion has important ramifications for both electronic and emerging photonic switching systems since it reduces the importance of the costly design feature of optimal scheduling.     

Statistical estimation of delay-dependent switching activities inembedded CMOS combinational circuits

This paper describes a new procedure to estimate the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical approaches to take advantage of their time-efficiency over conventional event-driven simulation tools. For this study, combinational circuits driven by discrete-time logic signals are considered. By focusing on a specific class of combinational circuits, the transitional effects can be analyzed more accurately by considering some of the delay effects neglected in previous studies, Also, to model the delay-dependent effects, statistical properties such as the pattern probability, the propagation probability, and the distribution of the propagation delay of switching activities are defined and evaluated. The simulation results on benchmark circuits indicate that the proposed procedure significantly speeds up the estimation process in comparison to the conventional event-driven simulators. The reliability issues in the aspect of switching activities are briefly discussed     

基于开关选通控制网络的FED驱动电路设计

基于开关控制技术提出了一种开关选通电流型FED驱动电路。该驱动电路包括FET开关选通电路、数字视频锁存电路及PWM调制转换电路等部分,开关选通电路每8路构成一组,各组同步工作,既减少了电流源数量又保证了PWM脉冲有较大的占空比,PWM信号最大脉宽可达TH/8。采用本驱动电路使得在一行内只有1/8的像素数同时导通,有效降低了行扫描驱动电路的输出电流和功耗,同时相邻阴极依次导通减弱了极间电容影响,有利于改善PWM调制性能。     

High performance MOS integrated circuit using the ion implantation technique

Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 /spl Omega//spl times/cm substrate material and having 1-/spl mu/m channel length. Essential fabrication details and circuit behaviors are described.