Developing a high-level fault simulation standard

Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well     

Formal Methods in Designing Embedded Systems—the SACRES Experience

From automotive electronics to avionics, embedded systems are part of our everyday life, and developed societies are increasingly dependent on their reliability in operation. At the same time, current design practice is inadequate in coping with the challenge of constructing dependable embedded systems.SACRES is an experimental design environment aimed at the seamless development of embedded systems. It incorporates state-of-the-art industrial design tools and provides formal specification, model checking technology and validated code generation. These concepts have been integrated on the basis of the synchronous approach to reactive systems.As a result, synchronous compilation techniques have been enhanced, in particular as regards techniques for distributed code generation. Formal verification technology was advanced to increase efficiency, handle composed systems and cover some real-time aspects. The new approach of translation validation was developed and proven to work.Real bugs have been found even in well-tested models. It was demonstrated that a formal design including verification is often more efficient than testing. As a consequence, all user partners are committed to further introducing formal design and verification technology.This paper summarises the essential achievements of the project. It explains the results in terms of the basic ideas, the available tools and methodology, as well as the experience gained.     

Algorithms for automatic test-pattern generation

Three well-known algorithms for the automatic test pattern generation (ATPG) for digital circuits are the D algorithm, Podem, and Fan. The author introduces the concept of test generation and analyzes the way each algorithm uses search and backtracking techniques to sensitize a fault and propagate it to an observable point. The heuristics used to guide ATPG search and the notation used to represent circuit values are examined     

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.     

含存储器数字电路系统的自动测试生成

已有的数字电路自动测试生成(ATPG)软件没有存储器的结构模型，不支持对存储器电路的自动测试生成。该文分析了2类存储器的功能特征，提出了面向测试的ROM和RAM结构模型的建立方法，其中，ROM根据所储存的数据等效成组合电路模型， RAM利用新建立的RAMBIT基元等效成利于测试的时序电路模型。将其应用于ATPG软件中，解决了含存储器数字电路的自动测试生成问题。     

适用于并行操作的C语言程序测试工具ParCT

并行计算技术的飞速发展给软件测试带来了新的要求．并行软件测试可以分为基于进程内部的控制流测试和基于进程间相互关系的时序测试．文中所介绍的并行软件的测试工具——ＰａｒＣＴ （ｐａｒａｌｌｅｌＣ－ｌａｎｇｕａｇｅ ｔｅｓｔｉｎｇｔｏｏｌｓ）主要是面向控制流的．文中介绍了ＰａｒＣＴ的运作机制及其主要功能：通过对程序的动态测试得到测试的覆盖率、列出未覆盖分支以及对各个分支的访问频度,从而帮助用户完成对测试程度的评估并为用户设计新的测试用例提供目标．在此基础上,还对并行测试工具所面临的一系列新课题,诸如进程的实时跟踪、面向控制流的测试产生（ｔｅｓｔｇｅｎｅｒａｔｉｏｎ）算法、面向多线程的测试工具、并行程序的时序测试（ｔｉｍ ｉｎｇ ｓｅｑｕｅｎｃｅ ｔｅｓｔｉｎｇ）等,进行了一定程度的探讨     

Testing methodology: implications for the circuit designer

The complexity achievable within a custom chip or on a PCB loaded with standard combinational or sequential elements, even without the use of VLSI components such as microprocessors, requires the use of automatic methods for the generation of test patterns if the task is to be completed within an acceptable time and at an acceptable cost. This paper reviews the current status of some aspects of the test process as applied to such circuits, and of the principles of structured design methodologies intended to reduce the difficulties of test pattern generation (TPG). The paper starts by reviewing the fault models on which most automatic TPG (ATPG) methods are based, and goes on to discuss some of the available ATPG methods themselves. The problems involved in TPG for sequential circuits are briefly discussed to show the motivation behind structured design for testability using the scan-in scan-out (SISO) principle. The main implications of SISO are described, as are some of the applications of these principles to the construction of testable PCBs.     

基于蚂蚁路径的多故障诊断算法研究

提出了一种针对VLSI电路多故障ATPG(Automatic Test Pattern Generation)的新算法。该算法引入蚂蚁路径定义，将多个故障点的前向传榆和回溯归结到一条单一路径之上，从而解决了以往多故障ATPG算法中搜索重复导致的计算冗余问题。     

基于蚂蚁路径的时序电路故障诊断算法

提出了一种VLSI时序电路自动测试型生成(Automatic test pattern generation，ATPG)的新算法。传统ATPG算法采用局部状态转换图或收集门级电路的知识以及提取电路规则来解决时序电路ATPG的困难。本算法引入新的模型，着重解决了ATPG中的计算冗余问题。在蚂蚁路径模型的基础上，前向搜索得到了重建，故障点的前向传输和回溯归结到了单一路径之上．而该路径上可能分布着许多待测的故障点，从而改善了以往时序电路ATPG算法中搜索重复而导致的计算冗余问题，同时，最小测试向量的获取为数学定理所证明。最后在Benchmark电路上进行的与ILP算法的比较试验表明，本算法具备同样的故障覆盖率，且速度更快。     

VLSI并行测试生成系统的一种动态层次框架

随着VLSI技术的发展和计算机性能的提高,并行测试生成系统不仅必需而且可行,本文在总结已有并行技术的基础上,提出了并行测试生成系统的一种动态层次框架,并给出了一种实现方案。     

基于布尔可满足性的组合电路ATPG算法

布尔可满足性被深入研究并广泛应用于电子设计自动化等领域。该文提出了一种基于布尔可满足性的组合电路ATPG改进算法。在采用当前最新布尔可满足性求解程序加速策略的基础上,比如冲突驱动训练、冲突导向回跳和重启动技术等,引入电路结构信息来实现基于结构的分支决策。通过新增的电路结构信息层,布尔可满足性求解程序只需稍加修改,就能利用和及时更新此信息。最后给出的实验结果表明了算法的可行性和有效性。     

工具服务化集成中数据交互方式设计

针对当前工具服务化集成中数据交互普遍存在的语法异构和语义异构问题,本文设计了一种基于JSON格式的语法定义形式和基于通用词表的语义异构处理方法的数据交互方式,并对其实现方法和技术进行了详细的论述.最后,在一种软件开发工具服务化集成的实际案例中进行了实验,对所提出的数据交互方式进行了实现并对其有效性进行了验证.实验结果表明,所设计的数据交互方式较好地解决了上述两个问题,为工具集成提供了良好的数据交互基础.     

Robust scan-based logic test in VDSM technologies

The customer expects defect-free chips, at consumer prices, making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm² on a 0.18-μm die); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. The new availability of silicon real estate has transformed the design-for-testability environment. Implementing contemporary application-specific integrated circuit (ASIC) designs based on standard-cell and gate array technologies now requires design flows that incorporate DFT. Robust design for testability in very deep-submicron (VDSM) technologies is essential to volume manufacturing. The most common structural test method is scan-based logic test, which is now the backbone of manufacturing test. Using this method, commercial ATPG tools rely on test-mode reconfiguration of the circuit to a pseudo-combinational one, ensuring its access, controllability, and observability. Each state bit is transformed into a stage (either a flip-flop or master-slave latch pair) of a shift register or scan chain accessible from chip pins. The author points out ways to avoid pitfalls in implementing effect scan-based test. These include modifying register-transfer-level circuit representations for testability, using a single clock edge design, and providing clock control     

Cycle decomposition in NCL

In convention logic (NCL) circuits, cycles are the fundamental unit of data storage, roughly equivalent to combinational logic bounded by latches in clocked design. Implementing the various tools common to IC design flows, such as static timing analysis and scan insertion, requires accurately identifying these cycles. Threshold gates are the basic building blocks of NCL cycles. To date, mechanisms for automatically identifying relevant NCL circuit cycles have been lacking. The NCL analyzer solves the problem of automatically identifying cycles from a gate-level netlist. It does this by identifying the acknowledge signal feeding a register from its relative signal polarity and then finding the intersection of a forward and reverse circuit traversal. Although the NCL analyzer is currently a stand-alone tool, we expect it will become an integral part of nearly all NCL-specific tools - including static timing analysis, orphan checking, ATPG, and possibly synthesis.     

A test-pattern-generation algorithm for sequential circuits

A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported     

复杂混合信号SoC芯片的延迟测试

随着芯片集成度的持续提高以及制造工艺的不断进步,对测试覆盖率和产品良率的严格要求,需要研究新的测试方法和故障模型。基于扫描的快速延迟测试方法已经在深亚微米的片上系统（SoC）芯片中得到了广泛的使用。通过一款高性能复杂混合信号SoC芯片的延迟测试的成功应用,描述了从芯片对延迟测试的可复用的时钟产生逻辑的实现,到使用ATPG工具产生延迟图形,在相对较低的测试成本下,获得了很高的转换延迟和路径延迟故障覆盖率,满足了产品快速上市的要求。     

The mutating metric for benchmarking test

The monitoring of three ATPG tool parameters-fault coverage, test generation time, and test vector count-has improved test benchmarking over the years. Changing test dynamics, however, requires a different test metric. Over the past two decades, test automation has evolved from manually created patterns for designs with fewer than 100 gates to automated test pattern generation for designs with 10 million gates. At every stage, a benchmark has provided a comparison point for the technology. Benchmarks have played a significant role in improving test automation, and a metric appropriate to the state of the art at any given moment quantifies the technology on benchmarks. Metrics change as technology changes, and test has seen its own share of changes to the metrics. In this article, we examine the evolution of metrics and propose a metric for future evaluations of test technology     

Timing Constraints of Real-Time Systems: Constructs for Expressing Them, Methods of Validating Them

This paper examines timing constraints as features of realtime systems. It investigates the various constructs required in requirements languages to express timing constraints and considers how automatic test systems can validate systems that include timing constraints. Specifically, features needed in test languages to validate timing constraints are discussed. One of the distinguishing aspects of three tools developed at GTE Laboratories for real-time systems specification and testing is in their extensive ability to handle timing constraints. Thus, the paper highlights the timing constraint features of these tools.     

一个适于形式验证的ATPG引擎

自动测试产生(ATPG)不仅应用于芯片测试向量生成，也是芯片设计验证的重要引擎之一．提出了一种组合电路测试产生的代数方法，既可作为组合验证的ATPG引擎，又可用于通常的测试产生．该算法充分发挥了二叉判决图(BDD)及布尔可满足性(SAT)的优势，通过启发式策略实现SAT算法与BDD算法的交替，防止因构造BDD可能导致的内存爆炸，而且使用增量的可满足性算法，进一步提高了算法的效率．实验结果表明了该算法的可行性和有效性．     

An integrated automatic test data generation system

The Godzilla automatic test data generator is an integrated collection of tools that implements a relatively new test data generation method—constraint-based testing—that is based on mutation analysis. Constraint-based testing integrates mutation analysis with several other testing techniques, including statement coverage, branch coverage, domain perturbation, and symbolic evaluation. Because Godzilla uses a rule-based approach to generate test data, it is easily extendible to allow new testing techniques to be integrated into the current system. This article describes the system that has been built to implement constraint-based testing. Godzilla's design emphasizes orthogonality and modularity, allowing relatively easy extensions. Godzilla's internal structure and algorithms are described with emphasis on internal structures of the system and the engineering problems that were solved during the implementation.Parts of this research were supported by Contract F30602-85-C-0255 through Rome Air Development Center while the author was a graduate student at the Georgia Institute of Technology.