高阶Σ-Δ调制器的非理想特性分析与建模

文章对2-1-1级联结构的高阶Σ-Δ A/D调制器的非理想特性,包括时钟抖动、MOS开关噪声、比较器迟滞性、放大器的输入噪声、单位增益带宽和有限直流增益等,进行了分析,提出了基于Matlab的高层次建模方法.通过系统仿真确定关键的电路参数和性能指标,在较高层次指导A/D转换器的电路结构级和晶体管级设计.     

16位音频ADC非理想型Σ-Δ调制器的建模

对一款适于16位音频A/D转换器的Σ-Δ A/D调制器进行了系统级设计,考虑了影响调制器性能的各种非理想因素,建立了一整套噪声模型,并进行了仿真分析.将仿真结果与未考虑非理想因素的结果进行比较,可以看出,考虑了非理想因素的建模更能预测实际电路的性能,从而更好地为晶体管级电路设计做铺垫.     

Σ-Δ调制器的非理想特性建模与验证

Σ-Δ调制器是常用于混合信号电路中的一个关键模块.基于一个的二阶低通调制器,对包括非理想开关、色噪声模型、非线性运放直流增益和多比特量化器中的电容适配在内的非理想效应,进行了分析和建模.该调制器在HJTC 0.18μm工艺下实现并进行了流片测试.通过对行为级仿真和实际测试数据的对比,验证了提出的高层次建模方法,可以准确高效地指导调制器系统级和电路级设计.     

Σ-Δ调制器在SIMULINK下的噪声模型

为了满足在行为级对Σ-Δ调制器进行完整仿真的需要,提出了在SIMULINK环境下Σ-Δ调制器的噪声模型,包括采样时钟抖动、开关热噪声(kT/C噪声)、运算放大器的有限增益、有限带宽、压摆及饱和电压等非理想因素。在给出具体噪声模型的基础上,构造出二阶Σ-Δ调制器模型。通过仿真,验证了噪声模型的正确性。     

Σ-Δ调制器在非理想环境中的仿真

介绍了一整套Simulink模型,利用其可以对任何Σ-Δ调制器的性能进行详尽的仿真.给出的模型中考虑了大量Σ-Δ调制器的非理想因素,例如采样时钟抖动、kT/C噪声和运算放大器参数(噪声、有限增益、有限带宽、转换速率和饱和电压)等.针对每个模型给出了详尽描述和所有实现细节.文中所有仿真的对象为一典型的二阶SC Σ-Δ调制器结构.最后的仿真结果论证了仿真模型的正确性.     

非理想Σ-Δ调制器在SIMULINK下的行为级建模

根据数模混合电路各种实际非理想因素的影响,建立了一系列实现不同Σ-Δ数模转换调制器SIMULINK时域行为级非理想效果模型。和经典级联结构仿真模型相比,文中给出的模型加入了多级噪声整形结构,通过仿真和计算传递函数,分析了不同的非理想因素对于不同结构的影响。     

用于过采样Σ-ΔA/D转换器的Σ-Δ调制器

分析并讨论了过采样 Σ- Δ A/D转换器中一阶、二阶及高阶级联结构的 Σ- Δ调制器的性能特点 ,并编写 C语言程序进行行为级仿真 ,用 PSpice进行电路级仿真 ,利用 MATLAB工具对其结果进行分析。结果表明 ,Σ-Δ调制器具有噪声整形特性 ,可以提高基带内的信噪比 ,且三阶级联结构中 1 - 1 - 1结构性能最优。Σ- Δ调制器与过采样技术相结合可构成高精度、低成本的 A/D转换器。     

一种具有改进积分器结构的高阶Σ-Δ调制器

设计了一个五阶单回路Σ-Δ调制器,最高输入信号频率22kHz。通过改进积分器的结构,显著减小了开关电荷注入效应引起的调制器的谐波失真。整个电路采用0.6μmCMOS工艺设计。仿真显示,当采样频率为6MHz时,调制器的SNDR达到123dB,SNR超过125dB,满足18位A/D转换器的精度要求。     

一种高精度音频Σ-Δ调制器的研究

简要介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器.该电路采用Chartered 0.5 μm标准CMOS工艺实现,工作电源电压为5 V,在工作频率为6.144 MHz、过采样率为128时,输入带内信噪比可达107 dB.     

一种改进的开关电容Σ-Δ调制器的行为模型

提出了一个开关电容Σ-Δ调制器的行为级模型。该模型不仅考虑了通常非理想特性,包括取样的抖动、kT/C噪声、有限带宽、有限摆率、电荷注入,还考虑了对系统性也有很大影响的开关的非零、非线性导通电阻。提出的模型在Simulink中实现,并与Cadence SPICE的电路级仿真进行了比较验证,二者具有较好的一致性。     

Sigma-Delta小数分频频率综合器系统建模和仿真

行为级仿真平台的建立,可以对小数频率综合器的设计提供快速全面的时域仿真.重点分析了2/3多模可编程分频器和MASH结构调制器电路,并给出了一种计算环路滤波器参数的新型工程方法.建立了的Simulink仿真模型,可用于检验电路结构的正确性.     

Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

高速4阶Sigma-Delta调制器系统级设计及行为级仿真

对高速4阶级联开关电容Sigma-Delta调制器结构的设计进行了分析,利用MATLAB SIMULIK工具搜寻了系统优化参数,并通过系统行为级仿真对实际高速电路中存在的运算放大器非理想因素(例如有限增益、有限单位增益带宽等)和开关热噪声(KT/C噪声)等因素对系统特性可能产生的影响进行了仿真计算,在此基础上得到了系统设计对实际电路模块参数特性的基本要求,为实际实现高阶Sigma-Delta系统打下了基础.仿真结果表明在考虑到各种实际因素的条件下,64 MHz时钟32倍超采样条件下系统精度可以达到14 bits.     

一种新型的级联并行过采样∑Δ调制器结构

本文提出了一种基于时域交织技术的级联∑Δ调制器新结构,保留了原有时域交织结构的速度优势,克服了它的缺点,且电路简单,具有实用价值.对1-1级联、4路并行的情况进行模拟的结果表明:新结构比普通2阶∑Δ调制器,相同时钟速率下转换精度提高3bit,同样精度要求下转换带宽扩大一倍,对各路增益失配等电路非理想因素不敏感.     

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notchfrequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.     

一种快速的连续时间delta-sigma调制器设计方法

提出了一种快速的连续时间delta-sigma调制器设计方法.该方法在设计初期就对性能、功耗和面积进行总体考虑和权衡,减少反复过程,达到快速设计的目的.使用该方法,在较小的功耗和面积的限制下设计了一个用于音频的三阶连续时间电流模式delta-sigma调制器,证明了该方法的正确性和有效性.     

On the Stability Analysis of High Order Sigma-Delta Modulators

In this paper we present an approach for stability analysis of high order Sigma-Delta modulators. The approach is based on a parallel decomposition of the modulator. In this representation, the general N-th order modulator is transformed into decomposition of low order modulators, which interact only through the quantizer function. In the simplest case of the loop filter transfer function with real distinct poles, the low order modulators are N first order ones. The decomposition considered helps to extract the sufficient conditions for stability of the N-th order modulator. They are determined by the stability conditions of each of the low order modulators but shifted with respect to the origin of the quantizer function, because of the influence of all other low order modulators. The approach is generalized for the case of repeated poles of the loop filter transfer function.     

Electronic Implementation of Multirate Sigma-Delta Modulators Using CMOS Technologies

Multirating has been recently proposed to reduce the frequency rate of the first integrator(s) of a single-loop, or the first stage(s) of a cascade, Sigma-Delta modulator (SDM). This is a promising technique for the design of high speed, low-power modulators, as the first integrator (or stage) in the chain primarily determines the performances of the modulator, as well as its power consumption. This paper presents the first implementation of a 2nd-order multirate SDM, showing different circuit solutions. The experimental results obtained with a prototype in a standard 0.6 μm CMOS technology shows that different clock rates can be selected for each integrator of a SDM. Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion. Francisco Colodro was born in Peal de Becerro (Jaén), Spain, in 1968. He received the Ingeniero de Telecomunicación degree from the University of Vigo, Vigo, Spain, in 1992, and the Ph.D. degree from the University of Sevilla, Sevilla, Spain, in 1997. In 1992 he joined the Department of Electronics Engineering, University of Sevilla, where he is currently and Associate Professor. His research interests are in the architectural study of Σ Δ modulators, the implementation of ADCs based on Σ Δ modulators, and application of electronic circuits and systems to communication. Marta Laguna was born in Seville, Spain. She received the Telecommunications Engineering degree from the University of Seville in 2002. She is currently working toward the Ph.D. degree. Her doctoral work focuses on the design of continuous-time sigma-delta modulators. Since 2001, she has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an assistant teacher in 2004. Her research interests are high-speed analog-to-digital converters and sigma-delta modulators. Antonio Torralba (M'89–SM'02) was born in Sevilla, Spain, in 1960. He received the electrical engineering and Ph.D. degrees from the University of Sevilla in 1983, and 1985, respectively. Since 1983 he has been with the Department of Electronics Engineering, School of Engineering, University of Sevilla, where he has been Associate Professor in 1987, and Full Professor since 1996, leading a research group on mixed signal design. In 1999 he made a short stay at the Department of Electrical Engineering, NMSU, and he is presently in the Department of Electrical Engineering, TAMU for a Sabbatical stay. His interests include low-voltage analog circuits and systems, analog to digital conversion, Σ Δ modulators, and electronic circuits and systems with application to control and communication. In these fields he has published around 40 journal papers and more than 100 conference papers, and he holds 2 international patents.     

Stability and Performance of Single-Bit Sigma-Delta Modulators Operated in Quasi-Sliding Mode

Single-bit sigma-delta modulators operated in the quasi-sliding mode are investigated. Sufficient conditions for the existence and stability of this mode of operation are derived. The derived stability conditions, along with an accurate prediction of its performance, enable a high-order modulator to be exactly designed. A fifth-order modulator is designed to convert audio-band signals with an effective resolution of 20 bits to demonstrate the effectiveness of the proposed analysis and method of design.     

Effect of Mismatched Loop Delay in Continuous-Time Complex Sigma-Delta Modulators

Continuous-time (CT) complex $SigmaDelta$ modulators seriously suffer from delay in real and imaginary feedback paths. The mismatched loop delay results in a degradation of the signal-to-noise ratio. In this paper, analytical considerations of mismatched loop delay in CT complex $SigmaDelta$ modulators are presented. Discrete-time equivalent transfer functions to that of a CT complex loop filter are derived from continuous-discrete transformation in the complex signal domain. A solution for reducing or compensating the effect of mismatched loop delay is proposed.