Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

Lanthanum diffusion in the TiN/LaOx/HfSiO/SiO2/Si stack

Band edge Complementary Metal Oxide Semiconductor (CMOS) devices are obtained by insertion of a thin LaO_x layer between the high-k (HfSiO) and metal gate (TiN). High temperature post deposition anneal induces Lanthanum diffusion across the HfSiO towards the SiO₂ interfacial layer, as shown by Time of Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) and Atom Probe Tomography (APT). Fourier Transform Infrared Spectroscopy in Attenuated Total Reflexion mode (ATR-FTIR) shows the formation of La-O-Si bonds at the high-k/SiO₂ interface. Soft X-ray Photoelectron Spectroscopy (S-XPS) is performed after partial removal of the TiN gate. Results confirm La diffusion and changes in the La chemical environment.     

Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

In this paper, the threshold voltage instability characteristics of HfO₂ high-k dielectric are discussed. The results from various stress bias conditions including DC and AC with variations of frequency, duty cycle, and polarity provide additional insights into the intrinsic behavior and the trapping dynamics of high-k materials. A reduced threshold voltage shift was observed at higher frequency and lower duty cycle under AC positive unipolar stress compared to DC stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress. However, subthreshold swing changes were found to be negligible and fairly independent of stress frequencies and duty cycles under AC positive unipolar stress.When different polarity of stress, such as positive, negative, and bipolar stress was applied, it was observed that frequency and duty cycle dependencies were still valid in all three conditions. In contrast to positive stress, negative stress showed a decrease in the threshold voltage shift. Bipolar stress resulted in the highest threshold voltage instability, but the degradation in transconductance and subthreshold swing was actually smaller than those in negative unipolar stress. The bulk trap of HfO₂ dielectric, which is proportional to its physical thickness, is believed to be the primary factor for threshold voltage shift. AC unipolar operation would allow a higher 10-year lifetime operating voltage than the DC condition. In addition to experimental results, a plausible mechanism has been proposed.     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

在metal/high-k 栅叠层中插入Ti/TiN金属层实现远距离吸氧技术

High permittivity materials have been required to replace traditional SiO₂ as the gate dielectric to extend Moore’s law.However,growth of a thin SiO₂-like interfacial layer（IL） is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO₂ dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO₂ have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Impact of defects on the high-κ/MG stack: The electrical characterization challenge

The integration of high-κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high-κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high-κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high-κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO₂ controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high-κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.     

Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO₂ n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO₂ by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO₂ resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Breakdown spots of ultra-thin (EOT < 1.5 nm) HfO2/SiO2 stacks observed with enhanced—CAFM

In this work, the (gate) current versus (gate) voltage (I–V) characteristics and the dielectric breakdown (BD) of an ultra-thin HfO₂/SiO₂ stack is studied by enhanced conductive atomic force microscopy (ECAFM). The ECAFM is a CAFM with extended electrical performance. Using this new set up, different conduction modes have been observed before BD. The study of the BD spots has revealed that, as for SiO₂, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images. The height of the hillocks observed in the topography images has been considered an indicator of structural damage.     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.