A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A 10-/spl mu/W standby power 256K CMOS SRAM

A 32K/spl times/8-bit CMOS static RAM using titanium polycide technology has been developed. The RAM has a standby power of 10 /spl mu/W, an active power of 175 mW, and an access time of 55 ns. The standby power has been achieved by an optimization of polysilicon resistors in a memory cell. A digit line circuit controlled by three internal clocks contributes to reduction of active power. The cell size has been reduced to 89.5 /spl mu/m/SUP 2/ by using both a buried isolation and a polycide GND line. Furthermore a simplified address-transition detection circuit and a single data bus configuration result in a small layout area, thus offering a 40.7 mm/SUP 2/ die size.     

An 18 ns 4K/spl times/4 CMOS SRAM

A high-speed 11-mm/SUP 2/ 4K/spl times/4 CMOS static RAM fabricated developed. This circuit uses improved circuit techniques to with a single-polysilicon, single-metal process has been obtain a typical 18-ns access time with only 250 mW of active power. Among the topics discussed are the smallest single-polysilicon static RAM cell reported to date; the use of address transition assistance for equalization and boosting; a short-delay, positive-feedback boosted word line; high-speed predecoded row and column decoders; new fully compensated bit-line loads and column presence amps; and an easily implemented redundancy scheme using laser fusing techniques.     

A 90 ns 256K /spl times/ 1 bit DRAM with double-level Al technology

A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques.     

A 40 ns CMOS E/SUP 2/PROM

New high-performance CMOS circuit techniques have been developed and used to build an 8K E/SUP 2/PROM with an access time of 38 ns at 5 V. Using standard CMOS/SOS technology, the device dissipates only 0.8 mW quiescent power at 5 V and 60 mW at 1 MHz. A midpoint precharge and sense technique permits operation form a supply voltage of 4-12 V.     

A new circuit configuration for a single-transistor cell using Al-gate technology with reduced dimensions

A single-transistor memory cell in Al-gate technology with 2.5 /spl mu/m line width with a new circuit configuration is introduced. In this cell, the ground line of one cell and the word line of the cell opposite the bit line share the same line. This circuit configuration leads to memory cells having a bit density of 5720 bit/mm/SUP 2/ even though it uses a single layer metallization. The voltage conditions in this cell differ from those in conventional storage cells, but do not reduce the operation range of the new cell. As design and circuit studies have shown, a 32 kbit memory can be realized on a chip area of about 15.4 mm/SUP 2/, having an access time of 200 ns and a power dissipation of 500 mW.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

Two-13 ns-64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques

64K/spl times/1 and 16K/spl times/4 CMOS SRAMs which achieve an access time of 13 ns and less than 12-mA active current at 10 MHz are described. A double-metal 1.5-/spl mu/m p-well process is used. A chip architecture with local amplification improves signal speed and data integrity. Address stability detection techniques are introduced as a method of assuring full asynchronicity over a wide range of conditions. A chip-select speed-up circuit allows high-speed access from a power-down mode. A memory cell design is presented which has improved layout efficiency (area of 189 /spl mu/m/SUP 2/), yet provides a very high cell ratio of 3:1 for signal stability and margin. Experimental results are presented which demonstrate full performance under address skews and other asynchronous input conditions. High-speed enable access and address access are observed over a wide range of operating conditions.     

I/SUP 2/L timing circuit for the 1 ms-10 s range

An I/SUP 2/L timing circuit without external components is presented, which makes use of some specific I/SUP 2/L properties-operation at low power levels, light sensitivity, variable delay, and long maximum delay times. The circuit comprises 45 gates on a chip area of 0.3 mm/SUP 2/. It produces pulses from below 1 ms to more than 10 s which are inversely proportional to a single supply current. For this purpose, new methods for current splitting and amplification with I/SUP 2/L circuits are used. The temperature dependence of the output pulse width is better than 0.8 percent/K. If the circuit is irradiated by light, it produces pulses with a pulse width inversely proportional to the light intensity. For example, it can be used as an integrated exposure meter for all kinds of photographic applications.     

A 16K E/SUP 2/PROM using E/SUP 2/ element redundancy

A new LSI memory redundancy technique using E/SUP 2/PROM cells as the programmable element has been developed. Yield enhancement with this technique has been demonstrated using two redundant rows on a 16K E/SUP 2/PROM chip. This paper describes the structure and operation of the circuit blocks used, and how these circuits interface with the memory chip to produce the observed yield enhancement. The method for programming the redundancy elements is described, along with circuit advantages and capabilities unique to E/SUP 2/PROM redundancy. Device performance and yield enhancement for the 16K E/SUP 2/PROM are summarized.     

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A 30 ns 16K/spl times/1 fully static RAM

A fully static 16K/spl times/1 random access memory (SRAM) with significantly improved speed is discussed. Design innovations using conservative 2.5 /spl mu/m transistors and state-of-the-art double level poly (DLP) scaled NMOS technology were utilized to accomplish 30 ns address and chip select access times with an active power of 550 mW and standby power of 75 mW. A cost effective DLP process was developed using `shared' contacts in the cell. These `shared' contacts utilize second level poly to provide connection between the first poly level and moat, reduced the number of contacts per cell to four. The DPL cell size is 1.6 mil/SUP 2/ (1000 /spl mu/m/SUP 2/) which yields a bar size of 158/spl times/264 mil/SUP 2/ (4.0/spl times/6.7 mm/SUP 2/). In this fully static design a novel architecture was used to power down half of the X-decoders in the active mode using the AO address buffer signals. This technique allowed the use of power saved in the X-decoder to be distributed throughout the circuit to improve overall access times. One of the other major speed improvements came from utilizing column sense amps. The use of the column sense amp improves the overall speed by more than 20 percent. A write cycle of 30 ns has been achieved with a typical write pulse width of 10 ns.     

A high-speed ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time

An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family.     

High density COS/MOS 1024-bit static random access memory

A static 1024/spl times/1 self-aligned silicon-gate COS/MOS random access memory (RAM) has been developed using `self-registry' techniques to achieve high packing density. The techniques developed permitted a 7500 transistor COS/MOS memory circuit to be fabricated in a 0.134/spl times/0.168 in/SUP 2/ chip, with a 13.4 mil/SUP 2/ six transistor cell. Such packing density is approximately five times that of conventional metal-gate COS/MOS circuits. The merits of fabricating such devices using an advanced process technique based on all ion-implanted diffusions to enhance yields have also been studied.     

High-speed split-emitter I/SUP 2/L/MTL memory cell

Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM.     

The Schottky I/SUP 2/L technology and its application in a 24/spl times/9 sequential access memory

The Schottky I/SUP 2/L device and a two-level metal scheme have been used to fabricate a 24/spl times/9 sequential access memory. The T/SUP 2/L compatible chip has 1287 Schottky I/SUP 2/L gates, operates at 60 mA, and requires an area of 13200 mil/SUP 2/. Details of the Schottky I/SUP 2/L technology and its application in a 24/spl times/9 sequential memory are discussed.     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.