基于LABVIEW的光收发模组的测试平台及测试分析

文章以光发射组件TOSA和光接收组件ROSA为主要硬件,LABVIEW7.0为软件开发测试平台,对已组装好的光收发模组的性能进行测试,并分析不同温度下的测试眼图和数据结果,完成测试任务。最后对测试中存在的问题进行了总结和展望。     

基于LabVIEW的跳频组件测控平台研究

为了满足跳频组件研制过程的测控需求,通过对跳频组件的工作原理和测控需求的分析,提出了基于计算机控制的测控平台的实现方案,研究了测控平台的设计原理、硬件结构和软件设计流程,最后在LabVIEW环境下开发出了针对具体跳频类组件应用的测控平台.实验证明,该测控平台的应用提高了组件的调试、测试效率,且缩短了组件的开发周期,具有很好的推广应用价值.     

Correlation Between EUT Failure Levels and ESD Generator Parameters

Some system-level electrostatic discharge (ESD) tests repeat badly if different ESD generators are used. For improving repeatability, ESD generator specifications have been changed, and modified generators have been compared in a worldwide round robin test. The test showed up to 1 : 3 variations of failure levels. Multiple parameters that characterize ESD generators have been measured. This paper correlates the parameters to test result variations trying to distinguish between important and nonrelevant parameters. The transient fields show large variations among different ESD generators. A correlation has been observed in many equipment under tests (EUTs) between failure levels and the spectral content of the voltage induced in a semicircular loop. EUT resonance enhances the field coupling, and is the dominate failure mechanism. The regulation on the transient field is expected to improve the test repeatability.      

System-level design for test of fully differential analog circuits

Several designs for test techniques for fully differential circuits have recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in differential circuits. These techniques have not previously been verified experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures. The test chip is a fully differential fifth-order filter, and was fabricated on a 2-μm CMOS process. The test techniques implemented are derived from a system-level technique developed earlier. The test chip contains fault injection circuitry to emulate faults. Our results demonstrate that the FDAC is a viable design for test technique for analog circuits     

空间用元器件热真空试验评价方法研究

空间用元器件热真空试验是空间环境模拟试验中非常重要的一项试验,文章通过对空间用元器件热真空环境应力的分析,给出了不同轨道的温度范围以及不同真空度下空间用元器件的物理效应;对空间用元器件热真空试验评价方法进行了研究和探讨,在参照组件、分系统、整星热真空试验方法的基础上,提出了器件级热真空试验程序。介绍了已开展的DC/DC混合集成电路和双向收发器单片集成电路的热真空试验情况和试验结果。试验结果表明,通过热真空试验,可以对空间用元器件热真空环境下的性能和可靠性进行试验评价,为航天用户单位合理选用空间用元器件提供科学依据。     

垂直燃烧可燃性等级判定试验探讨

通过对GB 4943-2001中材料可燃性测试条款的理解和分析,进一步明确垂直燃烧可燃性等级判定测试中对样品的要求和结论判定,对样品数量、合格判定条件、重复试验等标准中容易引起歧义的描述做了说明。     

电子应用产品的防电击试验浅析

本文依据国家有关标准对电子应用产品的防电击试验进行了简介和分析，指出了试验中应注意的问题。     

Shielding Tests for Cables and Small Enclosures in the 1- to 10-GHz Range

Electromagnetic shielding tests in the 1- to 1O-GHz frequency range have been characterized by lack of repeatability and reliability. New test methods have been developed which correct most of the causes of erratic behavior and have been found to provide reasonably smooth curves when results are plotted against frequency. Study of the results obtained under various conditions of test indicates that the test procedures approach the desired goal of providing a measure of shielding effectiveness that is related only to the test item itself. The cable test procedures are usable with any type of shielded cable including multiple conductor cables with connectors not intended for RF usage. Cables may be tested in their final configuration without need for modification or removal of insulation, etc. Results are given for tests made under various conditions and are compared with results obtained previously with the triaxial test method. Evaluation of the test procedure for testing small shielded enclosures was performed by testing suitable boxes equipped with leakage openings that could be moved to various points on the surface of the box. The results indiate that the general effect on shielding of a particular type of opening remains much the same regardless of its location or orientation. Results are given for a number of opening designs under various conditions of test.     

Investigation of interfacial delamination of a copper-epoxy interface under monotonic and cyclic loading: modeling and evaluation

Interfacial delamination is of important concern for multilayered microelectronic packages, as it is one of the most common failures observed after reliability test. Most of the work, available in open literature, focus on delamination propagation under monotonic loading rather than delamination propagation under cyclic loading. Interfacial fracture mechanics based methodologies have been proven to be efficient in handling interfacial delamination problem under monotonic loading. In this paper, the principles of interfacial mechanics have been applied in the analysis of interfacial fatigue crack propagation. Fatigue test has been conducted in studying onset of delamination and fatigue crack propagation (FCP) of an interfacial crack along a copper-epoxy interface. Models developed in this study have also been applied in the evaluation of multilayered integrated substrate test vehicles.     

再循环自净型排风柜检测方法的分析研究

在分析常规检测方法弊端的基础上,提出以环己烷、异丙醇或盐酸溶液代替SF6作为示踪气体,将吸附过滤器吸附量检测和控制浓度检测有机结合起来的一种改良检测方法;并从必要性、技术性和经济性角度分析了该检测方法用以检测再循环自净型排风柜的可行性和合理性。     

Yield Learning and Process Optimization on 65-nm CMOS Technology Accelerated by the Use of Short Flow Test Die

Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric/contact loops of a 65-nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.     

二维离散系统的频域稳定性检验定理

本文提出的二维离散系统的频域稳定性检验定理可用于任意阶次的二维离散系统稳定性检验，本文定理的检验算法可避免环路积分从而减少了计算量提高了检验精度。     

GaAs高速电路在片瞬态测试技术研究

介绍了ＧａＡｓ高速集成电路在片瞬态参数测试的技术原理和系统组成。利用该系统对部分ＧａＡｓ高速电路进行的测试结果表明, 该系统行之有效     

唯一性检测在椭圆偏振光谱薄膜拟合中的应用

利用椭圆偏振光谱进行薄膜样品的测量数据分析拟合时,薄膜厚度与介电常数具有很强的关联性。不同色散模型的选取也会对拟合结果产生明显的影响,引起较大误差。介绍了唯一性检测在椭偏拟合中的实现方法。并以二氧化钛样品为例,利用唯一性检测对比了不同色散模型、不同厚度、不同测量波段、不同入射角度时的唯一性检测结果。结果表明,唯一性检测能够有效标定出椭偏测量和拟合过程中所产生的误差,同时能够对不同色散模型进行量化对比,提升拟合精度。     

金属化层表面状况的不同处理方法对陶瓷金属封接强度的影响

针对陶瓷金属封接,分别采取了打磨法和酸洗法两种不同的方法对陶瓷金属化层的表面状况进行处理,得到了两种不同的表面状态。利用划痕测试法,分析比较了两种方法制备试验件表面的电镀镍层的结合力情况。进行抗拉实验,研究比较了采用两种不同方法处理后的陶瓷抗拉试验件的封接强度。研究表明,酸洗法对金属化陶瓷表面的处理可以使金属化层得到更为良好的表面状态,是一种可以提高陶瓷金属封接强度的有效可行的方法。     

路由协议测试研究—边界网关路由协议BGP—4测试

现有测试理论和方法在路由协议测试中面临挑战。由于路由协议具有与通信协议不同的特点,现有测试系统的能力已经难以满足测试需求,本文介绍了在路由协议测试中进行的探讨和实践,深入分析了路由协议的特点,在此基础上对现有测试方法的适用性进行考察,选择了相应的测试方法和结构,扩充了测试系统中的考实现增强测试能力,设计了TTCN格式的测试集,通过测试实践,证实所用方法手段的有效性,并为国产路由器的开发提供了有力的支持。     

宽带电路交换核心芯片的验证与测试

介绍了一种宽带电路交换核心芯片的结构,针对设计的电路给出了验证模型,讨论了功能验证的内容和方法,重点讨论了流片完成后如何对芯样片进行全面测试.给出了测试系统的组成,并对测试的步骤、内容和方法进行了讨论,最后给出了测试结果及其分析.芯片现已投入实际应用.     

STEAC: A Platform for Automatic SOC Test Integration

The lack of electronic design automation tools for system-on-chip (SOC) test integration increases SOC development time and cost, so SOC test integration tools are important in the success of promoting SOC. We have stressed practical SOC test integration issues, including real problems found in test scheduling, test input/output (I/O) reduction, timing of functional test, scan I/O sharing, etc. In this paper, we further consider the requirement of integrating at-speed testing of embedded cores - to detect timing-related defects, our test architecture is equipped with at-speed test capability. Test scheduling is done based on our test architecture and test access mechanism, considering I/O resource constraints. Detailed scheduling further reduces the overall test time of the system chip. All these techniques are integrated into an automatic flow to facilitate SOC test integration. The test integration platform has been applied to both academic and industrial SOC cases. The chips have been designed and fabricated. The measurement results justify the approach - simple and efficient, i.e., short test integration cost, short test time, and small hardware and pin overhead.     

A redundancy test-time reduction technique in 1-Mbit DRAM with amultibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M×1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test     

Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays

A novel test approach for interconnect resources(IRs)in field programmable gate arrays (FPGA)has been proposed.In the test approach,SBs (switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.