电气柜逻辑测试仪通信系统

主要对地铁电气柜逻辑功能测试仪通信系统进行了研究和设计. 电气柜逻辑测试仪通信模块包括两部分: 系统层和管理层的通信以及管理层和测试层的通信. 在电气柜逻辑测试仪中, 系统层和管理层的通信数据量大、频率高, 采用CAN总线通信方式, 而管理层和测试层的通信距离近, 数据少, 采用RS485通信. 在硬件设计的基础上, 又设计了通信软件, 经现场调试, 设计的通信模块能够实现系统间的可靠通信.     

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.     

基于RFC2544测试的网络测试仪的设计与实现

RFC2544是当前网络互联设备性能测试普遍使用的标准。该文设计并实现了一种支持RFC2544测试的性价比较高的网络测试仪。介绍了RFC2544标准及其测试条件,通过对网络测试仪硬件结构以及软件设计的说明,阐述了该系统的工作原理,结合相关测试条件,与国外产品进行比对测试,实验结果的量化误差表明了该系统测试的精确性。     

Testing logic-intensive memory ICs on memory testers

Presents Lotom, a tool which converts logic test vectors into memory test patterns and generates a corresponding memory test program for use on an economical memory tester. The authors report a sample time savings of 99% over manual conversion     

The 68040 processor. 2. Memory design and chip

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed     

Deterministic bit-stream digital neurons

In this paper, we present the design of a deterministic bit-stream neuron, which makes use of the memory rich architecture of fine-grained field-programmable gate arrays (FPGAs). It is shown that deterministic bit streams provide the same accuracy as much longer stochastic bit streams. As these bit streams are processed serially, this allows neurons to be implemented that are much faster than those that utilize stochastic logic. Furthermore, due to the memory rich architecture of fine-grained FPGAs, these neurons still require only a small amount of logic to implement. The design presented here has been implemented on a Virtex FPGA, which allows a very regular layout facilitating efficient usage of space. This allows for the construction of neural networks large enough to solve complex tasks at a speed comparable to that provided by commercially available neural-network hardware.     

PCM检查器的设计与实现

ＰＣＭ检查器从外部总线ＲＳ－４２２或者总线ＡＲＩＮＣ４２９上接收串行数据，经过处理后按照指定格式通过ＤＭＡ方式中断方式并行传送到ＰＣ存计器，详细描述了ＰＣＭ检查器的功能。体系结构和自测试设计，并用ＦＰＧＡ加以实现，最后总结了一些有效利用ＦＰＧＡ资源的经验。     

基于忆阻器的计算存储融合体系结构研究进展

Memristor is an enabling device with non volatile resistance, low power consumption, high durability, ease of integration, and CMOS compatibility. The stateful logic of memristors can rea lize the true fusion of computing and storage, and is complete in logic, which is expected to break the limitation of Von Neumann architecture and effectively alleviate the memory wall bottleneck. These excellent properties gain memristors great interest from academia and industry. In light of this, this paper summarizes the research progress of application oriented computing storage fusion architecture based on stateful logic. Firstly, the implementation principle and improvement method of state logic are analyzed in detail. Secondly, the state logic design based on the memristor crossbar is reviewed, including the parallel implementation of the basic logics, copy operation and comparison operation, and then the design principle and implementation structure of the data storage structure based on the memristors are summarized. The paper then revisits an application oriented computing storage fusion architecture in detail, and finally summarizes the problems in the research of this direction, and looks forward to the future direction.     

基于USB总线的边界扫描测试主控系统的设计

分析了边界扫描测试技术的工作机制对测试主控系统的功能需求。提出了一种基于USB总线的低成本边界扫描测试主控系统的硬件设计方案;该系统以便携式计算机为平台,用FPGA实现JTAG主控器生成满足IEEE1149．1协议的边界扫描测试信号,并用普通的SRAM实现存储器共享;该系统可以对系统级、PCB级和芯片级集成电路进行边界扫描测试以及进行边界扫描测试的研究和实验;通过试验,系统性能满足设计要求。     

飞针测试机:结构、原理与实现

介绍了一种测试PCB裸板性能的设备-飞针测试机,包括测试机的结构、测试的方法和原理随后简要介绍了飞针测试计算机控制系统的硬件和软件实现;最后应用旅行商问题的解决方法,对飞针测试探针移动路径的优化问题进行了研究.     

基于ActiveX Scripting技术的测试软件开发

测试软件(Tester)的开发不同于一般的软件开发,在测试软件开发的过程中,涉及到测试软件本身和测试用例(Testcase)两者之间的划分和协作。目前的测试用例脚本大都是一些自定义的格式文本,通过测试软件的分析来执行测试逻辑,不仅需要编写大量复杂的脚本解析程序,而且难以阅读和维护。为了解决这个问题,提出了一种基于ActiveX Scripting技术的测试软件开发方法,该方法可以将测试逻辑按照需求分配到测试软件和测试用例,提供了一种统一的编程接口,易于学习和使用。     

飞针测试机:结构、原理与实现

介绍了一种测试PCB裸板性能的设备-飞针测试机,包括测试机的结构、测试的方法和原理;随后简要介绍了飞针测试计算机控制系统的硬件和软件实现;最后应用旅行商问题的解决方法,对飞针测试探针移动路径的优化问题进行了研究。     

Flying Probe Tester : Architecture, Principle and Implementation

1 IntroductionThere are mainly three kinds of circuit faults:components' fault, PCB' s (Printed Circuit Board)fault and assemblage fault. Among them, PCB' s faultaccounts for half of all. Generally speaking, PCB' sfault comes into being in the manufacturing process andthe most common forms of the fault include the short ofconductors in different nets and the open of conductorsin the same net. There will be economy loss if we solderthe electron components on a PCB with fault. So, it isve…     

Design and implementation of dual processor block with shared external cache memory

The availability of low cost, high performance microprocessors has led to various designs of shared memory multiprocessor systems. As a result, commercial products which are based on shared memory have been proliferated. Such a multiprocessor system is heavily influenced by the structure of memory system and it is not difficult to find that most configurations include local cache memories. The more processors a system carries, the larger local cache memory is needed to maintain the traffic to and from the shared memory at reasonable level. The implementation of local cache memories, however, is not a simple task because of environmental limitations. In particular, the general lack of board space availability presents a formidable problem. A cache memory system usually needs space mostly to support its complex control logic circuits for the cache itself and network interfaces like snooping logic circuits for shared bus. Although packaging can be made denser to reduce system size, there are still multiple processors per board. It requires a more area-efficient cache memory architecture. This paper presents a design of shared cache for dual processor board of bus-based symmetric multiprocessors. The design and implementation issues are described first and then the evaluation and measurement results are discussed. The shared cache proposed in this paper has been determined to be quite area-efficient without the significant loss of throughput and scalability. It has been implemented as a plug-in unit for TICOM, a prevalent commercial multiprocessor system.     

无损检测中基于模糊逻辑的多传感器数据融合

模糊逻辑在多传感器数据融合中得到广泛的应用，但是基于模糊逻辑的多传感器数据融合在无损检测中的应用还是一个崭新的课题，本文给出了一种新的用于无损检测数据融合的模糊逻辑结构，并且给出了隶度函数以及运算符的定义，最后给出了例子阐明了这种结构在无损检测中的应用。     

一种基于总线的多处理器共享内存机制

基于总线的分布式多处理器体系结构是目前常见的高性能路由器硬件体系结构,清华大学计算机系统在研制“863”重大项目“高性能安全路由器”的过程中,在基于CompactPCI总线的PowerPC多处理器平台上实现了一种多处理器共享内存机制,该共享内存机制（SM机制）实现了一系列核心对象,包括SM内存,SM信号量,SM消息队列和SM任务控制块等,本文详细介绍了SM机制的设计与实现并给出了性能测试结果。     

A parallel logic system on a multicomputer architecture

This paper describes the implementation of a logic programming language on a massively parallel architecture. This implementation is based on the AND/OR Process Model which allows the exploitation of both AND and OR parallelism in logic programs. A distributed memory model is used, and a decentralized control mechanism has been designed. The multicomputer, which the system has been implemented on, consists of a network of Inmos Transputers. The AND/OR processes are implemented as Occam processes mapped onto the Transputer nodes. After the presentation of the system architecture and a deep discussion of the distributed memory management, some preliminary performance results are discussed.     

多播3-Omega交换网的设计思想

阐述了具有最佳硬件复杂度且可无阻地在输入/输出间传输任意多播信号的多播3-Omega网的设计思想，设计理念可表述为“置换-复制-置换”，组成形式为“Omega-1+Omega+Omega-1”。它具有O(nlogn)的硬件代价，存储空间和时间复杂度均为O(nlogn)，连接建立时间为(logn)，传输延迟O(logn)，符合Shannon的硬件代价极限标准，具有良好的可实现性。     

Parallel computers for advanced information processing

An overview is given of ESPRIT project 415, which involved the study of object-oriented, functional, and logic programming styles in six subprojects. The parallel languages and architectures designed to implement them are described, and the technology of the object-oriented approach pursued by the authors' team is examined. Their design includes a novel language, decentralized memory architecture, and system software