Integrated-optical multichannel wavelength multiplexer for monomode systems

A new concept of an integrated-optical multichannel wavelength multiplexer for single-mode-fibre systems is presented. The operation principle of the cascaded multiplexer is based on the periodic wavelength dependence of the two-mode-interference (TMI) in a two-mode waveguide, which is adiabatically coupled to single-mode waveguides. The multiplexer is analysed analytically and numerically (BPM), and is realised experimentally by using Ti: LiNbO3 channel waveguides.     

光纤光栅和环行器构成的多路光分插复用器

讨论由光纤光栅和光环行器构成的光分插复用器的结构,性能和特点,提出采用一段刻有多个光纤布拉格光栅的光纤,两个光环行器,WDM复用器和解复用器等器件,构造能够对WDM的多个信道实施分插操作的光分插复用器,该光分插复用器的插入损耗要比简单地把多个单路的光分插复用器进行级联时小得多,波分复用全光网络中的光分插复用技术,是实现波分复用网络的关键技术之一。     

Multichannel video and IP signal multiplexing system using CWDM technology

This paper describes how coarse wavelength-division multiplexing can realize a multiplexed multichannel video and Internet protocol (IP) system. In the proposed configuration, each signal is optically amplified separately to extend the service area. The IP signals are boosted by cost-effective erbium-doped fiber amplifiers, which have a simple configuration optimized for single-channel use. Two multiplexer/demultiplexer configurations are described. The proposed configurations yield a contents distribution network that offers bidirectional IP service in addition to the multichannel video service, which is transmitted as an analog signal. This paper presents an experiment that confirms the feasibility of this proposed system.     

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively     

Monolithic integrated 4:1 multiplexer and demultiplexer operating up to 4.8 Gbit/s

The letter describes the high-speed performance of a 4:1 time-division MSI multiplexer and demultiplexer, which are fabricated using advanced super self-aligned process technology (SST). The maximum operation speed of the multiplexer is 5.02 GHz under 576 mW power dissipation. The system, which is composed of a multiplexer and a demultiplexer, operates at up to 4.80 GHz. The demultiplexer has a power dissipation of 1148 mW. Interchannel interference is also examined.     

基于分立衍射光栅的波分复用(解复用)器

波分复用(解复用)器是光通信中重要的无源器件。对目前常用的波分复用(解复用)技术进行了综述,着重介绍了一种新颖的波分复用(解复用)技术,基于分立衍射光栅的波分复用(解复用)技术,并介绍了它所克服的技术难点以及目前它所达到的技术水平。     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

基于MPEG-2传输流的复用与解复用分析

本文介绍了MPEG-2系统层中TS流结构,以及与其相关的PSI信息,详细阐述了复用、解复用器的功能和实现,最后指出了复用及解复用器实现中的所遇到的问题和解决方法。     

AVS标准系统层介绍及复用的实现

在介绍AVS标准的系统部分的基础上,阐述了与MPEG-2标准系统部分的联系与区别.给出了一种易于实现的以帧为单位打PES分组包的复用方法,实现了完全符合AVS标准的传输流和节目流的复用.并且,利用AVS系统部分与MPEG-2系统部分的高度兼容性,给出了一种成本极其低廉的实现AVS音视频数据流复用解复用的方法.该方法完全不需要研制AVS复用解复用设备,而是利用现有的MPEG-2复用解复用设备就实现了AVS标准的传输流和节目流的复用.     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

Design and simulation of single-source single-electron complementary 4-bit multiplexing nano-circuits

The Single-Electron Transistor (SET) and Linear Threshold Gate (LTG) are among the basic functional Single-Electron Nano-Devices (SENDs). In this paper, these basic SENDs are used to design a single-source (SS) single-electron (SE) complementary 4-bit (4–1) multiplexer. This design is compared with the previously reported multiple-source SE complementary 4-bit multiplexer. The first reported SS SE complementary 4-bit demultiplexer is also introduced. The detailed schematic diagrams as well as the corresponding simulation results of the designed SE 4-bit multiplexer/demultiplexer (using SIMON 2.0 and SECS Monte Carlo SE simulators) are illustrated. The simulation results include input, control, and output signals; free energy and stability diagrams; and maximum allowed signal frequency. The estimated delay and energy consumption is calculated and presented.     

An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

A novel ultracompact two-mode-interference wavelength division multiplexer for 1.5-/spl mu/m operation

A novel ultracompact 2/spl times/2 wavelength division multiplexer (WDM) for 1.55-/spl mu/m operation based on highly dispersive two-mode interference (TMI) was designed, theoretically modeled, and verified using a finite-difference-time-domain (FDTD) method. A two-moded waveguide assisted with a dispersive tooth-shaped grating provided a mode-dependent reflection band of central wavelength at 1.55 /spl mu/m. The wavelengths of 1538 and 1572 nm that were at the band edges and had the lowest reflection losses and relatively high dispersion were selected for wavelength multiplexing. The result showed that the wavelengths were separated by grating dispersion in a coupler length of 75 /spl mu/m which was much shorter than the required length of 1.1 mm in a regular TMI multiplexer of no grating. Insertion loss of about 1.7 dB and channel contrast of about 12 dB were achieved.     

AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems

The implementation of multigigabit-per-second optical communication systems requires many high-speed electronic circuit components that meet stringent performance requirements. Several important research prototype circuits for fiber-optic transmission, implemented in a baseline AlGaAs/GaAs HBT process, are discussed. These include a 20 Gb/s decision circuit, a 27 Gb/s 1:2 demultiplexer, a 30 GB/s 2:1 multiplexer, a 27 Gb/s 4:1 multiplexer, and a 11 Gb/s laser driver IC     

取样光栅的反射谱特性及其应用

本文基于取样光栅的独特反射谱特性,对其作为光子器件如DBR激光器、波分复用/解复器和光插分复用器的结构图作了探讨.通过比较得知,用取样光栅构成的新型光子学器件比用单纯的光纤光栅构成的光子学器件在未来的密集型波分复用(DWDM)光纤通信系统中更有实用价值.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

A 9.5-Gb/s Si-bipolar ECL array

A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

ASIC在光电合一光纤数字传输设备中的应用

介绍在光电合一光纤数字传输设备中使用专用集成电路实现二次群复／分接器的设计，讨论ASIC应用中接口技术的解决办法，并给出实验测试结果。     

SCM光通信系统用复合／解复合器的研究

本文介绍了一种用于副载波复用（ｓｕｂｃａｒｒｉｅｒｍｕｌｔｉｐｌｅｘｉｎｇＳＣＭ）光通信系统的副载波复合／解复合器电路组件的结构及设计方法，其中就组件内各子电路的特性分析与设计用基本理论进行了简要叙述。最后给出了典型硬件样品的几组实测特性结果。