A brain-controlled switch for asynchronous control applications

Asynchronous control applications are an important class of application that has not received much attention from the brain-computer interface (BCI) community. This work provides a design for an asynchronous BCI switch and performs the first extensive evaluation of an asynchronous device in attentive, spontaneous electroencephalographic (EEG). The switch design [named the low-frequency asynchronous switch design (LF-ASD)] is based on a new feature set related to imaginary movements in the 1-4 Hz frequency range. This new feature set was identified from a unique analysis of EEG using a bi-scale wavelet. Offline evaluations of a prototype switch demonstrated hit (true positive) rates in the range of 38%-81% with corresponding false positive rates in the range of 0.3%-11.6%. The performance of the LF-ASD was contrasted with two other ASDs: one based on mu-power features and another based on the outlier processing method (OPM) algorithm. The minimum mean error rates for the LF-ASD were shown to be significantly lower than either of these other two switch designs.     

OPSnet: design and demonstration of an asynchronous high-speed optical packet switch

This paper presents the results of the optical packet switched network (OPSnet) project, which investigated the design of an asynchronous optical packet switch suitable for the core of an optical transport network (OTN). The requirements for the switch were to control and route variable-length packets transmitted at bit rates beyond 100 Gbit/s. The subsystems and techniques used are analyzed and presented. Fast header encoding and passive decoding is based on the differential phase-shift keying (DPSK) method. The dual-pump four-wave mixing (d-p FWM) wavelength-conversion technique, in combination with an arrayed waveguide grating (AWG), is utilized for packet switching. An advanced and fully controllable mechanism for the packet-switch control is presented, which is implemented on field programmable gate array (FPGA) technology. The control wavelength is generated using a tunable laser, the actual wavelength and new header values are provided utilizing fast header recognition and look-up tables. The integration of the subsystems is discussed, and the results of a four-output port asynchronous packet-switch demonstrator operating at 40 Gbit/s are presented. Finally, the switch limitations are examined and design issues are discussed.     

基于USB接口的网络切换器系统设计

通过采用PDIUSBD12和AT89S52微处理器等器件设计网络切换系统。阐述了系统的总体设计思想及其层次结构,并给出了系统结构图。该系统采用USB总线接口形成网络切换系统,为工作人员能够同时安全的使用内部局域网与Internet网提供新的思路。     

基于USB接口的网络切换器系统设计

通过采用PDIUSBD12和AT89S52微处理器等器件设计网络切换系统。阐述了系统的总体设计思想及其层次结构，并给出了系统结构图。该系统采用USB总线接口形成网络切换系统，为工作人员能够同时安全的使用内部局域网与Internet提供新的思路。     

D/A conversion interface design for DMT-ADSL applications

For high-speed internet access, high-performance analog front-ends are needed, and data converters are one of the crucial building blocks in these bent-ends. In this article we will report on the modeling and design of a D/A conversion interface for a DMT (discrete multi tone)-based ADSL system that could be integrated into a complete CMOS analog front-end. We will discuss the DMT transmit spectrum and its impacts on data converters, we will focus on modeling and simulating of the whole D/A interface, and we will describe a test chip implemented in a 0.6 μm CMOS process     

On the design of asynchronous optical packet switch architectures with shared delay lines and converters

Optical packet switching (OPS) is a promising technology to enable next-generation high-speed IP networks. A major issue in OPS is packet contention that occurs when two or more packets attempt to access the same output fiber. In such a case, packets may be dropped, leading to degraded overall switching performance. Several contention resolution techniques have been investigated in the literature including the use of fiber delay lines (FDLs), wavelength converters (WCs), and deflection routing. These solution typically induce extra complexity to the switch design. Accordingly, a key design objective for OPS is to reduce packet loss without increasing switching complexity and delay. In this paper, we investigate the performance of contention resolution in asynchronous OPS architectures with shared FDLs and WCs in terms of packet loss and average switching delay. In particular, an enhanced FDL-based and a novel Hybrid architecture with shared FLDs and WCs are proposed, and their packet scheduling algorithms are presented and evaluated. Extensive simulation studies show that the performance of proposed FDL-based architecture outperforms typical OPS architectures reported in the literature. In addition, it shown that, for the same packet loss ratio, the proposed hybrid architecture can achieve up to 30% reduction in the total number of ports and around 80% reduction in the overall length of fiber as compared to the FDL-based architectures.     

The package integration of RF-MEMS switch and control IC for wireless applications

The integration of microelectromechanical systems (MEMS) switch and control integrated circuit (IC) in a single package was developed for use in next-generation portable wireless systems. This packaged radio-frequency (RF) MEMS switch exhibits an insertion loss under -0.4 dB, and isolation greater than -45 dB. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or field effect transistor (FET) switches and consumes less power. The RF MEMS switch chip has been integrated with a high voltage charge pump plus control logic chips into a single package to accommodate the low voltage requirements in portable wireless applications. This paper discusses the package assembly process and critical parameters for integration of MEMS devices and bi-complementary metal oxide semiconductor (CMOS) control integrated circuit (IC) into a single package.     

Sliding mode control design principles and applications to electricdrives

The basic concepts, mathematics, and design aspects of variable-structure systems as well as those with sliding modes as a principle operation mode are treated. The main arguments in favor of sliding-mode control are order reduction, decoupling design procedure, disturbance rejection, insensitivity to parameter variations, and simple implementation by means of power converters. The control algorithms and data processing used in variable structure systems are analyzed. The potential of sliding mode control methodology is demonstrated for versatility of electric drives and functional goals of control     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

Network control method and human-machine interface design for ISDNmultimedia terminals

A human-machine interface has been created for an integrated services digital network (ISDN) network control unit (I-NUU). I-NUI is a sophisticated terminal device that allows a voice communication channel and two data channels to be connected through an ISDN I-series interface. ISDN communication functions and network control operations were analyzed to determine the required characteristics of I-NCU. I-NCU features the minimum number of control buttons and a liquid crystal display. Visual and audible information are used to keep the operator fully informed about the state of the communication channels     

Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications

Power consumption is a major concern for wireless sensor networks (WSNs) nodes, and it is often dominated by the power consumption of communication means. For such networks, devices are most of the time battery-powered and need to have very low power consumption. Moreover, for WSNs, limited amount of data are periodically sent and then the radio should be in idle or deep sleep mode most of the time. Thus using event-triggered radios is well suited and could lead to significant reduction of the overall power consumption of WSNs. Therefore this paper explores the design of an asynchronous module that can wake up the main receiver when another node is trying to send data. Furthermore, we implement the proposed solution in an FPGA to decrease the fabrication cost for low volume applications and make it easier to design, re-use and enhance. To decrease the static power consumption, we explore the possibility of reducing the supply voltage. The observed overall power consumption is under 5 μW at 250 kbps. Moreover, using a new asynchronous design technique, we observed that power consumption can be further reduced.     

Surface-discharge switch design: the critical factor

Dielectric properties that are critical to designing a long-life surface-discharge switch (SDS) are investigated. Theory is correlated with experiment by evaluating the performance of a large group of polymeric and ceramic dielectrics. These dielectrics are tested in a single-channel, self-commutating SDS operating at ~35 kV and ~300 kA (oscillatory discharge) with a pulse length of ~20 μs (1/4 period ~2 μs). The performance of a dielectric is characterized by its shot-to-shot breakdown voltage and by its mass erosion. Theoretically, the voltage holdoff degradation resistance (HDR) and the arc melting/erosion resistance (AMR) of a dielectric can be qualitatively predicted from its formativity and its impulsivity, respectively. The formativity and impulsivity are figures of merit calculated from the known thermophysical properties of the dielectric. The effects produced in dielectric performance by choice of electrode material (e.g., molybdenum, graphite, and copper-tungsten) and discharge repetition rate are also discussed     

无源光网络PON上联组网设计及业务保护应用

本文对无源光网络组网结构及其承载业务流量特征进行了调查,针对OLT上联口不同业务分别选择不同的业务冗余保护方式进行了研究。报告了当前较为常见的冗余保护技术以及组网应用,对基于不同业务的常用保护应用和组网设计进行了探讨总结,并讨论了特殊冗余保护技术的应用。组网设计只有和具体业务相结合,才能有效的实现业务质量提升和保障网络稳定。     

An optimal signal design for band-limited asynchronous DS-CDMAcommunications

An optimal signal design for band-limited, asynchronous, direct-sequence code-division multiple-access (DS-CDMA) communications with aperiodic random spreading sequences and a conventional matched filter receiver is considered in an additive white Gaussian noise (AWGN) channel. With bandwidth defined in the strict sense, two optimization problems are solved under finite bandwidth and zero interchip interference constraints. First, a chip waveform optimization is performed given the system bandwidth, the data symbol transmission rate, and the processing gain. A technique to characterize a band-limited chip waveform with a finite number of parameters is developed, and it is used to derive optimum chip waveforms which minimize the effect of multiple-access interference (MAI) for any energy and delay profile of users. Next, a joint optimization of the processing gain and the chip waveform is performed, given the system bandwidth and the data symbol transmission rate. A sufficient condition for a system to have lower average probability of bit error for any energy profile is found, and it is used to derive some design strategies. It is shown that the flat spectrum pulse with the processing gain leading to zero excess bandwidth results in the minimum average probability of bit error. Design examples and numerical results are also provided     

简化离线式开关电源的设计

开关电源的使用日益普及,电视机、机顶盒和录像机均采用这种方式供电,移动电话充电器、PDA(个人数字助理),甚至一些电动牙刷都采用开关电源。     

Crosspoint switch equipped with an interface for serial opticalinterconnection

A crosspoint switch was developed that has an interface for serial optical interconnection. By using optoelectronic devices, cascaded switching was achieved through serial optical interconnection up to a bit rate of 10 Gb/s     

Hybrid control system design using a fuzzy logic interface

A hybrid control system is proposed for regulating an unknown nonlinear plant. The interface between the continuous-state plant and the discrete-event supervisor is designed using a fuzzy logic approach. The fuzzy logic interface partitions the continuous-state space into a finite number of regions. In each region, the original unknown nonlinear plant is approximated by a fuzzy logic-based linear model, then state-feedback controllers are designed for each linear model. A high-level supervisor coordinates (mode switching) the set of closed-loop systems in a stable and safe manner. The stability of the system is studied using nonsmooth Lyapunov functions. For illustration and verification purposes, this technique has been applied to the well-known inverted pendulum balancing problem.     

基于C#的OPC自动化接口异步访问技术

主要阐述在C#语言环境中编程,实现了通过SimaticNet提供的OPC Server自动化接口异步访问PLC中数据的技术。经过测试,高效率完成了对PLC数据读写的过程,解决了两个平台间的无缝迁移问题。     

DIRSMIN: a fault-tolerant switch for B-ISDN applications usingdilated reduced-stage MIN

We have developed and analyzed a dilated high-performance fault-tolerant fast packet multistage interconnection network (MIN). This new switch, (d,d')-DIRSMIN, uses dilation to improve performance and fault-tolerance of a network. The links at the input and output stages of the dilated banyan-based MIN are rearranged to create multiple routes for each source-destination pair in the network, after removing the first stage in the network. These multiple paths are link- and node-disjoint. This new MIN can provide low packet-loss probability and high reliability with very little hardware overhead, compared to d-dilated banyan networks (BN). Fault tolerance at low latency is achieved by transmitting multiple copies of each input-packet simultaneously using different routes. A multiple-priority scheme allows alternate paths to be explored simultaneously, which results in higher throughput and reliability under both fault-free and faulty conditions. This guarantees that high throughput is maintained even in the presence of a fault. Throughput is analyzed using analytic and simulation methods; this new design has considerably higher performance in the presence of a permanent faulty switching-element (SE) or link, in comparison to dilated networks. Under non-faulty conditions, both analytic and simulation results show that a (d,d)-DIRSMIN performs better than the original dilated BN with the same SE complexity. We analyze the network reliability and show that the new design has superior reliability compared to competing proposals. In particular, this new design is considerably better than the SEN+, the best known thus far