Low frequency noise in SiGe-base heterojunction bipolar transistors and SiGe-channel metal oxide semiconductor field effect transistors

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.     

An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse falling time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed.     

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method.     

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.     

Bias temperature instabilities in 4H SiC metal oxide semiconductor field effect transistors: Insight provided by electrically detected magnetic resonance

We present insight with regard to the physical mechanisms of negative bias temperature instabilities (NBTI) in 4H SiC based metal oxide semiconductor field effect transistors (MOSFETs) based upon electrically detected magnetic resonance measurements (EDMR). Most of this insight results from EDMR studies not directly focused upon NBTI but studies more broadly focused upon two fundamental questions. (1) What as-processed defects are present at and near the SiC/oxide interface? (2) How does the presence of oxide charge alter electrically active defects at the SiC/dielectric interface? We compare the SiC results to magnetic resonance studies of bias temperature instabilities in silicon based devices. Although our analysis admittedly provides only a partial understanding of the phenomena in SiC devices, the analysis does allow for some reasonably definitive conclusions. The NBTI phenomena in 4H SiC MOSFETs are certainly different than in Si based MOSFETs. (1) Interface dangling bonds do not appear to play a significant role in SiC MOSFET interface traps under multiple circumstances, suggesting strongly that they are not significant contributors to NBTI. (2) Although oxide defects, almost certainly including the well-known E′ family of oxide traps, play an important role in SiC device NBTI, other defects, surprisingly including defects within the SiC substrate, are also involved.     

A comparison of radiation tolerance of field effect and bipolar transistors

An analytical comparison of the radiation tolerance of conventional silicon field effect transistors and of silicon bipolar transistors has been performed. The channel or base thickness has been used as the respective critical variable, since it measures the degree of difficulty of device fabrication. For field effect transistors, the pinch-off voltage has been used as a free parameter. Based on recent lifetime degradation data for bipolar transistors and on carrier removal data for material of variable resistivity, it is shown that field effect transistors are not inherently more radiation tolerant than bipolar transistors. Only field effect transistors with pinch-off voltages well in excess of 10 volts appear superior to bipolar transistors.     

N and P metal oxide semiconductor field effect transistor characteristics of hafnium-doped SiO2 gate dielectrics

This work presents the interfacial properties of hafnium-doped SiO₂ films via N and P metal oxide semiconductor (MOS) materials, MOS-capacitor, and N and P metal oxide semiconductor field effect transistor (MOSFET) characterization. The results indicate that HfSi_xO_y films (a) have excellent transistor characteristics; (b) remain amorphous through high-temperature processing; (c) are compatible with N+ and P+ polysilicon electrodes; (d) have lower gate leakage than SiO₂ of the same equivalent oxide thickness (EOT); and (e) have a dielectric constant of ∼8. Therefore, the hafnium-doped SiO₂ films are at-tractive as a dielectric material and offer a technologically relevant gate-stack node for insertion, prior to deployment of high-K dielectrics.     

Persistent photoconductivity in AlGaAs/GaAs modulation doped layers and field effect transistors: A review

The phenomenon of persistent photoconductivity in AlGaAs/GaAs modulation-doped layers and transistors is reviewed. Experimental observations, mechanisms which are responsible for it and structures for its elimination are discussed.     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.     

Effect of the discharging and recharging of the stress generated oxide charge in metal–oxide–semiconductor capacitors on the low field leakage current

Low field leakage currents, through thin gate oxides of metal-oxide-semiconductor capacitors, increase after negative high field stress. We have observed that this increase could be reduced and even suppressed if the trapped holes created by the stress were neutralized by application of low voltage pulses. We have also observed that these pulses had the effect of making the recharge of the stress created slow states more and more difficult.     

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.     

Evolution in crystal structure and electrical performance of thiophene-based polymer field effect transistors: A remarkable difference between thermal and solvent vapor annealing

We report the various conformational structures of long pendant side-chains, and the effects of thermal and solvent vapor annealing (SVA) with the corresponding charge carrier mobilities of thiophene-based conjugated polymers, poly[5,5′-bis(3-dodecyl-2-thienyl)-2,2′-bithiophene] (PQT-12) and poly(4,4′-bis-decyloxymethylquaterthiophene) (POQT), by correlated study of their extraordinary polymorphic crystal structures. In substitution for alkyl chains in polythiophenes, ether alkyl chains induce a favorable non-covalent interaction between the oxygen and sulfur atoms and help the polymer chains planar with lower torsion angles between conjugated backbone units showing a reduced π–π stacking distance. However, the flexibility and conformational freedom with such long side-chains dominantly induce polymorphic crystallites from bent and extended side-chains. Especially, POQT exhibit two polymorphic crystallite phases in a similar ratio probably due to the increased freedom of ether alkyl chains. Therefore, the field effect mobility of POQT is decreased gradually with the increase of annealing temperature from 0.024 (at 80 °C) to 3.96 × 10⁻⁴ cm²/V s (at 170 °C). Contrary to the thermal annealing method, solvent-vapor-annealed POQT films show highly ordered and single-phase crystallites with edge-on orientation to the substrate, which ultimately provides an effectively improved charge carrier mobility from 0.023 (pristine) to 0.076 cm²/V s after adequate solvent vapor exposure.     

A comparison of performance of three orthogonal polynomials in extraction of wide-band response using early time and low frequency data

The objective of this paper is to generate a wideband and temporal response of three-dimensional composite structures by using a hybrid method that involves generation of early time and low-frequency information. The data in these two separate time and frequency domains are mutually complementary and contain all the necessary information for a sufficient record length. Utilizing a set of orthogonal polynomials, the time domain signal (be it the electric or the magnetic currents or the near/far scattered electromagnetic field) could be expressed in an efficient way as well as the corresponding frequency domain responses. The available data is simultaneously extrapolated in both domains. Computational load for electromagnetic analysis in either domain, time or frequency, can be thus significantly reduced. Three orthogonal polynomial representations including Hermite polynomial, Laguerre function and Bessel function are used in this approach. However, the performance of this new method is sensitive to two important parameters-the scaling factor l/sub 1/ and the expansion order N. It is therefore important to find the optimal parameters to achieve the best performance. A comparison is presented to illustrate that for the classes of problems dealt with, the choice of the Laguerre polynomials has the best performance as illustrated by a typical scattering example from a dielectric hemisphere.