Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.     

低复杂度FIR数字滤波器设计方法

FIR滤波器具有绝对稳定性和线性相位的优势,然而当对滤波器的频域性能要求较高时,FIR滤波器通常需要很高的阶数,这使得FIR滤波器硬件执行的复杂度很高。为降低FIR滤波器的硬件执行复杂度,诸多研究者进行了探索。文章对低复杂度FIR滤波器设计方法进行研究,着重介绍比较典型的频率响应罩设计方法、外插脉冲响应设计方法和基于压缩感知的设计方法。     

Polynomial-Based Interpolation Filters—Part I: Filter Synthesis

This paper introduces a generalized design method for polynomial-based interpolation filters. These filters can be implemented by using a modified Farrow structure, where the fixed finite impulse response (FIR) sub-filters possess either symmetrical or anti-symmetrical impulse responses. In the proposed approach, the piecewise polynomial impulse response of the interpolation filter is optimized directly in the frequency domain using either the minimax or least mean square criterion subject to the given time domain constraints. The length of the impulse response and the degree of the approximating polynomial in polynomial intervals can be arbitrarily selected. The optimization in the frequency domain makes the proposed design scheme more suitable for various digital signal processing applications and enables one to synthesize interpolation filters for arbitrary desired and weighting functions. Most importantly, the interpolation filters can be optimized in a manner similar to that of conventional linear-phase FIR filters.     

基于分段查找表的高速FIR滤波器的设计实现

提出了一种基于分段查找表的高速FIR滤波器的实现结构,该结构可应用于任意阶数的高速FIR滤波器设计中。采用分段查找表代替传统的乘法器、在加法输出级中插入流水线,以提高滤波器的工作速度;同时,通过数据预处理和查找表复用技术,降低了硬件开销。该设计方法已应用于射频识别超高频阅读器接收端的低通滤波器设计中,性能经Altera Stratix II FPGA测试后,可得到最高工作频率为170.44 MHz,比传统结构的提高了96.44 MHz,且硬件资源消耗较少,约为传统结构的三分之一。     

基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

Implementation of Digital Unbiased FIR Filters with Polynomial Impulse Responses

This paper addresses the design and implementation of digital unbiased finite impulse response (FIR) filters with polynomial impulse response functions. The transfer function, its fundamental properties, and a general block-diagram are discussed for the impulse response represented with the l-degree Taylor series expansion. As a particular results, we show a fundamental identity uniquely featured to such filters in the transform domain. For low-degree impulse responses, the transfer functions are found in simple closed forms and represented in compact block-diagrams. The magnitude and phase responses are also analyzed along with the group delays. A comparison with predictive FIR filters is given. As examples of applications, filtering of time errors of local clocks is discussed along with the low-pass filter design employing a cascade of the unbiased FIR filters.     

Design techniques for silicon compiler implementations ofhigh-speed FIR digital filters

Architecture design techniques for implementing both single-rate and multirate high throughput finite impulse response (FIR) digital filters are explored, with an emphasis on those which are applicable to automated integrated circuit layout techniques. Various parallel architectures are examined based on the criteria of achievable throughput versus hardware complexity. Well-known techniques for reduced complexity and computation time are briefly summarized, followed by the introduction of several new techniques which offer further gains in both throughput and circuitry reduction. An architecture for mirror-symmetric polyphase filter banks is derived which exploits the coefficient symmetry between multiple filters to reduce hardware. Finally, the evolution of a silicon compiler which utilizes all of these techniques is presented, and results are given for compiled filters along with comparisons to other compiled and custom FIR filter chips     

通信系统中FIR数字滤波器的设计研究

文中基于FPGA技术设计了一个16阶FIR数字低通滤波器。采用分布式算法作为滤波器的硬件实现算法。通过将FIR滤波器的乘加运算转化为查找表,极大提高了FIR滤波器的速度。在程序设计中采用了层次化、模块化的设计思想,将整个滤波器划分为多个功能模块。仿真结果表明：文中设计的滤波器硬件规模较小。同时只要将查找表进行相应的改动,就能分别实现低通、高通、带通FIR滤波器,体现了设计的灵活性。     

快速傅立叶变换辅助设计数字低通滤波器

详尽讨论了快速傅立叶变换(FFT)应用于有限冲击响应(FIR)数字低通滤波器(DLPF)的设计和分析方法.应用FFT算法,将理想DLPF幅频特性转换到变换域,获得其变换域序列;设计窗函数对该序列开窗,获得FIR有限序列;应用快速傅立叶逆变换(IFFT)对其进行变换,获得相应窗函数可实现DLPF幅频特性.结果发现,FFT算法可获得与传统卷积算法相同的结果;不需要推算窗函数的频谱解析表达式;可以处理Kaiser窗等变换域解析式复杂、频域解析式难以精确求解的窗函数设计与分析.与传统的卷积分析法相比,FFT不仅算法简单、灵活,而且处理能力强,是分析FIR DLPF设计的有力工具.     

升余弦滤波器的快速设计与FPGA实现

介绍了一种升余弦滤波器的快速设计方法,利用Matlab设计滤波器的冲击响应,通过采样量化编码,得到在FIR Compiler加载的系数文件;FPGA中调用FIR Compiler,采用分布式算法实现该滤波器结构,并在ISE中进行综合、实现。     

Equiripple FIR filter design by the FFT algorithm

The fast Fourier transform (FFT) algorithm has been used in a variety of applications in signal and image processing. In this article, a simple procedure for designing finite-extent impulse response (FIR) discrete-time filters using the FFT algorithm is described. The zero-phase (or linear phase) FIR filter design problem is formulated to alternately satisfy the frequency domain constraints on the magnitude response bounds and time domain constraints on the impulse response support. The design scheme is iterative in which each iteration requires two FFT computations. The resultant filter is an equiripple approximation to the desired frequency response. The main advantage of the FFT-based design method is its implementational simplicity and versatility. Furthermore, the way the algorithm works is intuitive and any additional constraint can be incorporated in the iterations, as long as the convexity property of the overall operations is preserved. In one-dimensional cases, the most widely used equiripple FIR filter design algorithm is the Parks-McClellan algorithm (1972). This algorithm is based on linear programming, and it is computationally efficient. However, it cannot be generalized to higher dimensions. Extension of our design method to higher dimensions is straightforward. In this case two multidimensional FFT computations are needed in each iteration     

B-spline design of maximally flat and prolate spheroidal-type FIRfilters

A digital FIR filter is described that offers excellent passband and stopband characteristics for general applications. Design formulae include parameters that adjust the magnitude response from one having characteristics like the maximally flat designs of Hermann (1971) and Kaiser (1975, 1979) to one having characteristics like the minimum-sidelobe energy approximations of Kaiser and Saramaki (1989). The impulse response coefficients are more straightforward to obtain than these filter designs while offering preferable response characteristics in many instances. Unlike FIR filters designed by window- or frequency-sampling methods, the filter coefficients are determined from the inverse Fourier transform in closed form once B-splines have been used to replace sharp transition edges of the magnitude response. Although the filters are developed in the frequency domain, a convergence window is identified in the convolution series and compared with windows of popular FIR filters. By means of example, adjustment of the transitional parameter is shown to produce a filter response that rivals the stopband attenuation and transition width of prolate spheroidal designs. The design technique is extended to create additional transitional filters from prototype window functions, such as the transitional Hann window filter. The filters are particularly suitable for precision filtering and reconstruction of sampled physiologic and acoustic signals common to the health sciences but will also be useful in other applications requiring low passband and stopband errors     

Frequency domain design of FIR and IIR Laplacian of Gaussian filters for edge detection

This work addresses the design of LoG filters in the frequency domain within a structure formed by the cascade of quasi-Gaussian and discrete Laplacian filters. The main feature of such a structure is that it requires half the number of convolutions of the classical structure in which the LoG transfer function is expressed as the sum of two separable transfer functions of 1-D Gaussian and LoG type. Such a perspective allows one to rephrase the design of IIR and FIR filters for edge detection as a frequency domain approximation problem solvable by standard digital filter design tools. The zero-phase IIR solutions have a good performance at low orders and approximation errors practically independent of the aperture parameter. The characteristics of the nearly linear-phase IIR filters solving the problem suggest the consideration of linear-phase FIR filters with zeros constrained on the unit circle. The use of such filters leads to remarkable computational savings with respect to the filters designed by impulse response sampling. The agreement between the edge values obtained by the filters designed according to the scheme proposed in this work and those obtained by standard techniques is very good.Work carried out with the financial support of the C.N.R.-Progetto Finalizzato Robotica, contract no. 91.01942.PF67.     

A Novel Diversity-Controlled Genetic Algorithm for Rapid Optimization of Bandpass FRM FIR Digital Filters Over CSD Multiplier Coefficient Space

The conventional frequency response masking (FRM) approach is one of the most well-known techniques for the design of sharp transition band finite impulse response (FIR) digital filters. The resulting FRM digital filters permit efficient hardware implementations due to an inherently large number of zero-valued multiplier coefficients. The hardware complexity of these digital filters can further be reduced by representing the remaining (non-zero) multiplier coefficient values by using their canonical signed-digit (CSD) representations. This paper presents a novel diversity-controlled (DC) genetic algorithm (GA) for the discrete optimization of bandpass FRM FIR digital filters over the CSD multiplier coefficient space. The resulting bandpass FIR digital filters are permitted to have equal or unequal lower and upper transition bandwidths. The proposed DCGA is based on an indexed look-up table of permissible CSD multiplier coefficients such that their indices form a closed set under the genetic operations of crossover and mutation. The salient advantage of DCGA over the conventional GA lies in the external control over population diversity and parent selection, giving rise to a rapid convergence to an optimal solution. The external control is achieved through the judicious choice of a pair of DCGA optimization parameters. An empirical investigation is undertaken for choosing appropriate values for these control parameters. The convergence speed advantages of the DCGA are demonstrated through its application to the design and optimization of a pair of bandpass FRM FIR digital filters with equal or arbitrary lower and upper transition bandwidths. In both cases, an increase of about an order of magnitude in the speed of convergence is achieved as compared to the conventional GAs.     

A fast design algorithm for elliptic-error and phase-error constrained LS 2-D FIR filters

Two-dimensional (2-D) nonlinear-phase finite impulse response (FIR) filters have found many applications in signal processing and communication systems. This paper considers the elliptic-error and phase-error constrained least-squares design of 2-D nonlinear-phase FIR filters, and develops a matrix-based algorithm to solve the design problem directly for the filter’s coefficient matrix rather than vectorizing it first as in the conventional methods. The matrix-based algorithm makes the design to consume much less design time than existing algorithms. Design examples and comparisons with existing methods demonstrate the effectiveness and high efficiency of the proposed design method.     

Efficient 2-D based algorithms for WLS designs of 2-D FIR filters with arbitrary weighting functions

The impulse response coefficients of a two-dimensional (2-D) finite impulse response (FIR) filter naturally constitute a matrix. It has been shown by several researchers that, two-dimension (2-D) based algorithms that retain the natural matrix form of the 2-D filter’s coefficients are computationally much more efficient than the conventional one-dimension (1-D) based algorithms that rearrange the coefficient matrix into a vector. In this paper, two 2-D based algorithms are presented for the weighted least squares (WLS) design of quadrantally symmetric 2-D FIR filters with arbitrary weighting functions. Both algorithms are based on matrix iterative techniques with guaranteed convergence, and they solve the WLS design problems accurately and efficiently. The convergence rate, solution accuracy and design time of these proposed algorithms are demonstrated and compared with existing algorithms through two design examples.     

Charge sampling analogue FIR filter

The finite impulse response (FIR) function of the proposed filter is realised by integrating weighted signal currents in a given time window on a capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such an FIR filter, the hardware cost is delinked to the number of taps.     

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.     

微波电路的时域设计方法

本文研究了几种微波电路或元件和FIR数字滤波器的直接结构形式的内在关系。从而将FIR数字滤波器的窗函数设计技术引用到微波电路的设计中,提出了这些微波电路的时域设计方法。该方法具有简捷,有闭合形式公式可循等优点,尤其适合于工程设计。     

Design of FIR filter ISOTA with the aid of genetic algorithm

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.