新型硅基双异质外延SOI材料Si/γ-Al2O3/Si制备

异质外延法是目前制备新型SOI材料的技术途径之一。采用低压化学气相沉积技术(LPCVD)在硅衬底上先外延γ-Al2O3绝缘单晶薄膜，制备出硅衬底上外延氧化物外延结构γ-Al2O3/Si(EOS)，然后采用类似SOS薄膜生长的常压CVD(APCVD)方法在EOS上外延硅单晶薄膜，形成新型硅基双异质SOI材料Si／γ-Al2O3／Si。利用反射高能电子衍射(RHEED)、X射线衍射(XRD)、俄歇电子能谱(AES)及MOS电学测量等技术表征分析了Si(100)／γ-Al2O3(100)／Si(100)SOI异质结构的晶体结构、组分和电学性能。测试结果表明，已成功实现了高质量的新型双异质外延SOI结构材料Si(100)／γ-Al2O3(100)／Si(100)，γ-Al2O3与Si外延薄膜均为单晶，γ-Al2O3薄膜具有良好绝缘性能，SOI结构界面清晰陡峭，该SOI材料可应用于CMOS电路的研制。     

基于薄膜SOI材料的GaN外延生长应力释放机制

本文研究了SOI衬底上采用MOCVD方法生长GaN材料的应力释放机制.采用SIMOX工艺制备的具有薄膜顶层硅的SOI材料作为外延生长的衬底材料,采用MOSS在位检测系统以及拉曼测试作为GaN内部应力的表征手段.结果表明,SOI材料对硅基GaN异质外延中的晶格失配应力和热应力的释放都有显著作用.薄膜SOI材料通过顶层硅与外延层的界面滑移,将一部分晶格失配应力通过界面的滑移释放,并且通过柔性薄膜顶层硅自身的应力吸收作用,将一部分热失配应力转移到衬底,从而有效地降低了GaN外延层的张应力.     

200mmBCD器件用硅外延片制备技术研究

本文涉及200 mm BCD(Bipolar-CMOS-DMOS)器件用硅外延片制备技术，通过结合BCD工艺用外延材料的特性要求，从外延图形漂移、外延层均匀性、表面缺陷等参数指标，分析了衬底埋层浓度、生长温度、生长速率、缓冲层结构等工艺参数对外延参数的影响，优化了BCD工艺用硅外延片的制备方法。本文采用常压化学气相沉积(CVD)技术制备了BCD工艺用200 mm硅(Si)外延材料，通过Hg-CV、SP1及SRP对埋层外延片进行测试分析，实验结果验证了工艺设计的正确性和有效性，提升了大尺寸埋层外延制备技术的产业化水平。     

硅基光电集成材料及器件的研究进展

以硅基光电集成回路为主线，综述了不同的硅基光波导材料的制备技术和硅基光波导的制作工艺及其对光传输损耗的影响。分析了硅基光波导与锗硅光探测器集成用两种不同的耦合方式，阐明了波导与探测器集成的机理及设计理论基础。归纳出硅基键合激光器的四种技术方案，指出其共同优点是克服材料异质外延引起的晶格失配和热膨胀非共容，对实现OEIC行之有效。     

新型硅基GaN外延材料的热应力模拟

采用有限元方法，通过ANSYS软件模拟了体硅衬底上和SOI衬底上生长的GaN外延膜从1100℃的生长温度降到20℃的热应力变化情况。模拟结果表明SOI衬底作为一种柔性衬底，能有效减少异质外延的晶格失配，但是单从热失配的角度，由于引入了热膨胀系数（CET）更小的埋层SiO2，SOI衬底会使得外延层热应力略有增大。为了降低外延层中的热应力，我们结合微机电系统（MEMS）的制造工艺，用深反应离子刻蚀（DRIE）的方法，借助于SOI材料自停止刻蚀的优势，将衬底硅和埋氧去除，使得SOI的超薄顶层硅部分悬空，形成一种新型的SOI衬底。模拟结果表明，这种新型SOI衬底可以将GaN外延层中的热应力降低20％左右。     

基于SOI光波导的损耗测试与优化

利用电子束光刻技术,制备了带有氧化硅包层的SOI光波导结构,对其传输模态及损耗进行了详细的理论分析,并分别对波导的传输损耗和耦合损耗进行了测试.测试结果验证了单模传输模态时的传输损耗较低,在波导层上添加覆盖层可以将波导传输损耗降低至3.96dB/cm,利用光栅垂直耦合可以大大降低光纤-波导的耦合损耗,耦合效率可以达到32.7%.     

利用UHV／CVD技术在双层多孔硅上外延硅研究

利用 UHV/CVD技术 ,在较低的温度下 ,在阳极氧化形成的双层多孔硅上 ,成功地生长了单晶性好、厚度均匀、电阻率分布合适的硅单晶外延层。这为进一步研制 SOI材料与器件提供了所需的薄硅外延层。     

多孔硅外延层转移制备SOI材料的研究

用多孔硅外延层转移的方法成功地制备出了SOI材料，卢瑟福背散射／沟道谱（RBS／C）和扩展电阻（SPR）的结果表明获得的SOI材料上层硅具有很好的单晶质量，电阻率分布均匀，上层硅与氧化硅埋层界面陡直。对制备多孔硅的衬底材料也作了研究，结果表明P型重掺杂的硅衬底在暗场下阳极氧化后仍保持很好的单晶性能，用超高真空电子束蒸发方法能外延出质量很好的单晶硅，并且，在一定浓度的HF／H2O2溶液中具有较高的腐蚀选择率，保证了上层硅厚度的均匀性。     

超薄SIMOX材料的Pseudo-MOSFET电学表征

介绍了一种表征SOI材料电学性质的手段,并对三种不同顶层硅厚度的SIMOX材料进行测试、提取参数,分析材料制备工艺对性能产生的影响。研究结果表明,标准SIMOX材料通过顶层硅膜氧化、腐蚀等减薄工艺制得的顶层硅厚度小于100nm的超薄SIMOX材料,其顶层硅与BOX层界面有更多的缺陷,会影响到在顶层硅膜上制得的器件的性能,引起NMOSFET的阈值电压升高、载流子迁移率降低。Pseudo-MOSFET方法能够在晶圆水平上快捷有效地表征超薄SIMOX材料的电学性质。     

一种新型SOI绝缘硅复合材料的制备与性能表征

提出了一种新型SOI绝缘硅材料及其制备方法。通过高温工艺制备SiO_2-Ta_2O_5-B_2O_3-RO复合粉体,以其为中间层,将上下两层单晶硅片在700～800℃熔凝从而获得Si-insulator-Si 3层结构体。结果表明该样品层间结合紧密、分布均匀,具有良好的高压绝缘性能和介电性能。其绝缘层厚度、深度和性能参数可调,是一种新型的厚膜SOI绝缘硅复合材料。     

Hydrogen annealing effects on epitaxy of SOI wafer

Thick silicon on insulator (SOI) wafers have been fabricated by chemical vapor deposition (CVD) after separation by implantation of oxygen (SIMOX) process. The hydrogen annealing effects on epitaxial Si layer were studied. The hydrogen annealing could remove the surface damages of substrate caused by SIMOX process and provide a smoother epitaxial substrate. The number of dislocations and stacking faults in the epitaxial layer decreased remarkably by hydrogen annealing SOI substrate. Meanwhile, compared with other reports, our hydrogen annealing did not degrade the buried oxide layer and top Si layer of SOI substrate.     

A study of Si epitaxial layer growth on SOI wafers prepared by SIMOX

The epitaxial Si layers were deposited onto silicon on insulator (SOI) substrates by chemical vapor deposition technology, and SOI substrates were manufactured with separation by implantation of oxygen technology. The dislocations and stacking faults of epitaxial Si layer and substrate were examined and their densities were calculated, respectively. The surfaces of epitaxial Si layer and SOI substrate were studied by atomic force microscopy. The SOI substrates and the epitaxial Si layers were characterized by Rutherford backscattering and channeling spectroscopy. Transmission electron microscopy was used to observe the defect in epitaxial layer. The result shows that the defects in the epitaxial Si layer on low dose substrate are less than those in the epitaxial Si layer on standard dose substrate, and also that the defects in low dose substrate are less than those in standard dose substrate. The crystallinity of epitaxial Si layer on low dose substrate is better than that of epitaxial Si layer on standard dose substrate.     

低能低剂量注水形成SOI结构材料的研究

采用无质量分析器的离子注入机，以低能量低剂量注水的方式替代常规SIMOX注氧制备SOI材料，测试结果表明，此技术成功地制备了界面陡峭，平整，表层硅单晶质量好的SOI结构材料，在剂量一定的条件下，研究不同注入能量对SOI结构形成的影响，使用剖面透射电镜技术（XTEM）和二次离子质谱技术（SIMS）等测试方法对注入样品和退火后样品进行分析，结果表明，表层硅厚度随注入能量增大不断增大；埋层二氧化硅厚度相对独立，仅在超低能（50keV)低剂量情况下厚度出现明显降低；埋层质量（包括界面平整度，硅岛密度等）与注入能量变化相关。     

Growth of oriented Ag nanocrystals on air-oxidized Si surfaces: An in-situ reflection high energy electron diffraction study

Growth of Ag nanoislands on air-oxidized Si(001), (111) and (110) surfaces has been investigated by reflection high energy electron diffraction (RHEED), scanning tunneling microscopy (STM) and cross-sectional transmission electron microscopy. We have shown that the oriented nanocrystalline Ag, similar to the epitaxial growth of Ag on clean Si surfaces, can be grown on oxide-covered Si surfaces. A thin oxide layer (~ 2-3 nm thick) is formed on ultra-high vacuum (UHV)-cleaned Si surfaces via exposure of the clean reconstructed surface to air. Deposition of Ag was carried out under UHV at different substrate temperatures and monitored by RHEED. RHEED results reveal that Ag deposition at room temperature leads to the growth of randomly oriented Ag islands while, in spite of the presence of the oxide layer between Ag islands and Si, preferred orientations with an epitaxial relationship with the substrate evolve when Ag is deposited at higher substrate temperatures. STM images of the oxidized surfaces, prior to Ag deposition, apparently do not show any order. However, Fourier transforms of STM images show the presence of a short range order on the oxidized surface following the unit cells of the underlying reconstructed Si surface. It is intriguing that Ag nanoislands follow an epitaxial orientational relationship with the substrate in spite of the presence of a 2-3 nm thick oxide layer between Ag and Si. Apparently, the short range order existing on the oxide surface influences the orientation of the Ag nanoislands.     

Transfer of single crystalline silicon nanolayer onto alien substrate

Starting from the 60-nm node, future generations of mainstream semiconductor devices (i.e., CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate, thus resulting in SOI. The process includes: 1) forming a trap layer for hydrogen in an initial substrate; 2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen; 3) evolving the trapped hydrogen into a layer of hydrogen platelets; 4) stiffening of the surface of the initial substrate by laminating to another substrate; and 5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process are described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver atomic hydrogen to the traps. Electron cyclotron resonance, microwave, RF, and dc plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are also described. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of the thickness of the layer that is transferred from one substrate to another. The scaling limit of our process is compared to the limits of other (SIMOX, Smart-Cut, and ELTRAN) processes.     

SiCOI structure fabricated by catalytic chemical vapor deposition

Epitaxial growth of SiC on SOI substrates using a hot-mesh chemical vapor deposition (CVD) technique was investigated. This technique utilizes a catalytic reaction involving hot tungsten wires arranged in a mesh structure. Using this hot-mesh CVD method, SiC epitaxial growth on SOI substrates with a thin top Si layer was realized without formation of voids, which form readily in the thin Si top layer at temperatures above 800 °C. The SiC film grown on an SOI structure exhibited a large gage factor (GF) of − 27, which is approximately the same as that (GF = − 31.8) of a SiC epitaxial film on Si(100) grown at 1360 °C using atmospheric pressure CVD.     

GaN epitaxial layers prepared on nano-patterned Si(001) substrate

We report the growth of GaN epitaxial layer on Si(001) substrate with nano-patterns prepared by dry etching facility used in integrated circuit (IC) industry. It was found that the GaN epitaxial layer prepared on nano-patterned Si(001) substrate exhibits both cubic and hexagonal phases. It was also found that threading dislocation observed from GaN prepared on nano-patterned Si(001) substrate was significantly smaller than that prepared on conventional unpatterned Si(111) substrate. Furthermore, it was found that we can reduce the tensile stress in GaN epitaxial layer by about 78% using the nano-patterned Si(001) substrate.     

SOI材料的缺陷及其表征

简述了利用注氧隔离法(SIMOX)制备的SOI材料中产生的一些不同于体硅材料的特殊缺陷,涉及表面缺陷、Si/SiO2界面缺陷和埋氧层缺陷,包括这些缺陷的产生机制、表征方法以及一些降低和消除措施.     

Asymmetry of the Defect Structure of Semipolar GaN Grown on Si(001)

The defect structure of a thick (~15 μm) semipolar gallium nitride (GaN) layer grown by hydride–chloride vapor phase epitaxy on a Si(001) substrate with buffer layers has been studied by transmission electron microscopy. The asymmetry of the defect structure of GaN epilayer has been revealed and analyzed. The influence of this asymmetry on the rate of decrease in the density of threading dislocations in the growing epitaxial layer is discussed.