Low-operation voltage of InGaN-GaN light-emitting diodes withSi-doped In0.3Ga0.7N/GaN short-period superlatticetunneling contact layer

InGaN/GaN multiple-quantum-well light-emitting diode (LED) structures including a Si-doped In_0.23Ga_0.77N/GaN short-period superlattice (SPS) tunneling contact were grown by metalorganic vapor phase epitaxy. In_0.23Ga_0.77N/GaN(n⁺)-GaN(p) tunneling junction, the low-resistivity n⁺-In_0.3Ga_0.77 N/GaN SPS instead of high-resistivity p-type GaN as a top contact layer, allows the reverse-biased tunnel junction to form an “ohmic” contact. In this structure, the sheet electron concentration of Si-doped In_0.23Ga_0.77N/GaN SPS is around 1×10¹⁴/cm², leading to an averaged electron concentration of around 1×10²⁰/cm³. This high-conductivity SPS would lead to a low-resistivity ohmic contact (Au/Ni/SPS) of LED. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 2.95 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V     

Recessed-gate AlGaN/GaN HFETs with lattice-matched InAlGaN quaternary alloy capping layers

In this paper, we present recessed AlGaN/GaN heterojunction field-effect transistors (HFETs) with lattice-matched InAlGaN capping layers, which reduce both ohmic contact resistance and series resistance between the AlGaN and the capping layer. The lattice-matched alloy epitaxial layer with both In and Al high compositions are successfully grown by metal-organic chemical vapor deposition. The grown lattice-matched In/sub 0.09/Al/sub 0.32/Ga/sub 0.59/N capping layer has close total polarization and bandgap to those of the underlying Al/sub 0.26/Ga/sub 0.74/N layer. The balanced polarization eliminates the depletion of electrons at the In/sub 0.09/Al/sub 0.32/Ga/sub 0.59/N/Al/sub 0.26/Ga/sub 0.74/N interface, which can reduce the series resistance across it. It is also noted that the fabricated HFET exhibits very low ohmic contact resistance of 1.0/spl times/10/sup -6/ /spl Omega//spl middot/cm/sup 2/ or less. Detailed analysis of the source resistance reveals that the series resistance at the In/sub 0.09/Al/sub 0.32/Ga/sub 0.59/N/Al/sub 0.26/Ga/sub 0.74/N interface is one fifth as low as the resistance at the conventional GaN/Al/sub 0.26/Ga/sub 0.74/N interface.     

InGaN/GaN LEDs with a Si-doped InGaN/GaN short-period superlattice tunneling contact layer

Nitride-based light-emitting diodes (LEDs) with Si-doped n⁺-In_0.23Ga_0.77N/GaN short-period superlattice (SPS) tunneling contact top layer were fabricated. It was found that although the measured specific-contact resistance is around 1 × 10⁻² Ω-cm² for samples with an SPS tunneling contact layer, the measured specific-contact resistance is around 1.5×10⁰ Ω-cm² for samples without an SPS tunneling contact layer. Furthermore, it was found that one could lower the LED-operation voltage from 3.75 V to 3.4 V by introducing the SPS structure. It was also found that the LED-operation voltage is almost independent of the CP₂Mg flow rate when we grow the underneath p-type GaN layer. The LED-output intensity was also found to be larger for samples with the SPS structure.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Highly reliable GaN-based light-emitting diodes formed by p-In/sub 0.1/Ga/sub 0.9/N-ITO structure

Indium-tin-oxide (ITO) is deposited as a transparent current spreading layer of GaN-based light-emitting diodes (LEDs). To reduce the interfacial Schottky barrier height, a thin p-In/sub 0.1/Ga/sub 0.9/N layer is grown as an intermediate between ITO and p-GaN. The contact resistivity around 2.6/spl times/10/sup -2/ /spl Omega//spl middot/cm/sup 2/ results in a moderately high forward voltage LED of 3.43 V operated at 20 mA. However, the external quantum efficiency and power efficiency are enhanced by 46% and 36%, respectively, in comparison with the conventional Ni-Au contact LEDs. In the life test, the power degradation of the p-In/sub 0.1/Ga/sub 0.9/N-ITO contact samples also exhibits a lower value than that of the conventional ones.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

Low dark current quasi-Schottky barrier MSM-photodiode structures on n-Ga/sub 0.47/In/sub 0.53/As with p/sup +/-Ga/sub 0.47/In/sub 0.53/As cap layer

The p/sup +/-cap layer was used to fabricate a metal-semiconductor-metal (MSM) interdigitated photodetector on Ga/sub 0.47/In/sub 0.53/As. The measured barrier height was Phi /sub Bn=/0.52 V, the ideality factor n=1.1 and average dark current density 2 mA/cm/sup 2/. A rise time of 45 ps at lambda =1.3 mu m under 2 V bias was measured for an MSM photodiode with 3 mu m finger width and finger gaps and an active area of 100*100 mu m/sup 2/.<>     

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.     

GeMoW refractory ohmic contacts to n-type GaAs with In/sub 0.5/Ga/sub 0.5/As cap layer

GeMoW is presented as a refractory ohmic contact to n-type GaAs with an In/sub 0./5Ga/sub 0.5/As cap layer. The contact exhibits ohmic behaviour over a wide annealing temperature range from 300 to 700 degrees C. A minimum contact resistance of 0.176 Omega mm was obtained following furnace annealing at 500 degrees C.<>     

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.     

Low-Temperature Ta/Al-Based Ohmic Contacts to AlGaN/GaN Heteroepitaxial Structures on Silicon Wafers

Semiconductors - The formation features of a low-temperature Ta/Al-based ohmic contact to Al0.25Ga0.75N/GaN heteroepitaxial structures on silicon substrates are studied. The fabricated ohmic...     

Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7//Si

We have studied the Ni and Co germano-silicide on Si/sub 0.3/Ge/sub 0.7//Si. The Ni germano-silicide shows a low sheet resistance of 4-6 /spl Omega///spl square/on both P/sup +/N and N/sup +/P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3/spl times/10/sup -8/ A/cm/sup 2/ and 2/spl times/10/sup -7/ A/cm/sup 2/ are obtained for Ni germano-silicide on P/sup +/N and N/sup +/P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.     

Evaluation of single ohmic metallisations for contacting both p- and n-type GaInAs

The contact resistivity of various non-alloyed ohmic contact metallisations on both n- and p-type Ga/sub 0.47/In/sub 0.53/As has been investigated. Pd/AuGe metallisation was found to be most suitable when layers of both doping types were to be contacted in a single step, having lower contact resistivities on p/sup +/-GaInAs than Ti/Pt/Au and AuBe/Pt/Au. On n/sup +/-GaInAs, the contact resistivity was found to be almost independent of the metallisation used.<>     

Avalanche noise characteristics of single Al/sub x/Ga/sub 1-x/As(0.3

Groves  C. Chia  C.K. Tozer  R.C. David  J.P.R. Rees  G.J. 《Quantum Electronics, IEEE Journal of》2005,41(1):70-75

AlGaN/GaN/InGaN/GaN DH-HEMTs with an InGaN notch for enhanced carrier confinement

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin In/sub x/Ga/sub 1-x/N(x=0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm/sup 2//V/spl middot/s and a sheet resistance of 420 /spl Omega//sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 14.5 GHz, and a peak power gain cutoff frequency (f/sub max/) of 45.4 GHz were achieved on a 1/spl times/100 /spl mu/m device. The off-state source-drain leakage current is as low as /spl sim/5 /spl mu/ A/mm at V/sub DS/=10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz.     

Room temperature performance of low threshold 1.34-1.44-/spl mu/m GaInNAs-GaAs quantum-well lasers grown by molecular beam epitaxy

Room temperature lasing emission at 1.338 and 1.435 /spl mu/m with threshold current densities of 1518 and 1755 A/cm/sup 2/, respectively, is obtained in broad area GaInNAs-GaAs laser diodes (LDs) grown by molecular beam epitaxy. The 1.338-/spl mu/m LDs show a power output per facet up to 0.20 W/A, a characteristic temperature (T/sub 0/) of 78 K, and an external transparency current density (J/sub tr/) of 0.77 kA/cm/sup 2/. Increasing the lasing wavelength to 1.435 /spl mu/m results in a larger J/sub tr/ of 1.16 kA/cm/sup 2/ and a lower T/sub 0/ of 62 K, due to larger nonradiative recombination. However, the 1.435-/spl mu/m LDs still display a power output per facet up to 0.15 W/A, and a high internal quantum efficiency of 52%. These improved performances are achieved without the need to use strain compensation layers, Sb as a surfactant during the quantum-well growth, or a postgrowth thermal anneal cycle.     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

Double heterojunction bipolar transistor in Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system

Double heterojunction bipolar transistors based on the Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system are examined. The base layer consists of narrow band gap GaAs/sub 1-y/Sb/sub y/ and the emitter and collector consist of wider band gap Al/sub x/Ga/sub 1-x/As. Preliminary experimental results show that AlGaAs/GaAsSb/GaAs DHBTs exhibit a current gain of five and a maximum collector current density of 5*10/sup 4/ A/cm/sup 2/.<>     

Reduction of 1/f noise in multiplexed linear In/sub 0.53/Ga/sub 0.47/As detector arrays via epitaxial doping

A significant (2-5*) reduction in 1/f noise was observed in In/sub 0.53/Ga/sub 0.47/As photodetector arrays read out by a PMOS multiplexer, when the epitaxial InP cap layer doping was changed from undoped to sulfur-doped n type of about 3*10/sup 16/ cm/sup -3/. A further decrease was observed when the InP buffer layer was also changed from undoped to sulfur-doped n type of about 5*10/sup 17/ cm/sup -3/. Data was presented for the variation of 1/f noise, within a temperature range of 18 degrees C to -40 degrees C. Surface states at the InP cap/SiN interface appears to be the primary source of 1/f noise, with the bulk states at the n/sup -/In/sub 0.53/Ga/sub 0.47/As buffer hetero-interface as a secondary source. Increased n-type doping in the high-bandgap InP cap and buffer layers may reduce electron trapping, and thus 1/f noise. The measured noise spectrum of InGaAs photodetectors varies as f/sup y/ with y being approximately -0.45 for device structures with doped and undoped InP can layers. For a doped InP buffer layer, this value of y is -0.3.<>     

Improved NiSi salicide process using presilicide N/sub 2//sup +/ implant for MOSFETs

An improved Ni salicide process has been developed by incorporating nitrogen (N/sub 2//sup +/) implant prior to Ni deposition to widen the salicide processing temperature window. Salicided poly-Si gate and active regions of different linewidths show improved thermal stability with low sheet resistance up to a salicidation temperature of 700 and 750/spl deg/C, respectively. Nitrogen was found to be confined within the NiSi layer and reduced agglomeration of the silicide. Phase transformation to the undesirable high resistivity NiSi/sub 2/ phase was delayed, likely due to a change in the interfacial energy. The electrical results of N/sub 2//sup +/ implanted Ni-salicided PMOSFETs show higher drive current and lower junction leakage as compared to devices with no N/sub 2//sup +/ implant.