Scaling the MOS transistor below 0.1 μm: methodology, devicestructures, and technology requirements

This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 μm. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 μm MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

Temperature dependency of 0.1 μm partially depleted SOI CMOSFET

This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 μm MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I_OFF) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs     

A study on channel design for 0.1 μm buried p-channel MOSFETs

This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 μm via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed the substrate with a doping concentration of 1e17/cm³. By optimizing the doping structure, an attempt is made to investigate fundamental limits of the buried channel design. In concurrence with published results, it is shown that there is a maximum allowable thickness for the first layer, while the thickness of the anti-punchthrough layer has a minimum value in order to effectively suppress punchthrough. The above constraints enable devices with good subthreshold characteristics (subthreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation results show that it is possible to fabricate buried p-channel MOSFETs with n-type polysilicon gate electrodes in the 0.1 μm regime, it is also evident that advanced doping and low temperature fabrication technologies are needed that provide control over doped layers of ultra-thin dimensions     

0.1 μm Schottky-collector AlAs/GaAs resonant tunneling diodes

The Schottky-collector resonant tunneling diode (RTD) is an RTD with the normal N+ collector and ohmic contact replaced by a Schottky contact, thereby eliminating the associated parasitic resistance. With submicron Schottky contact dimensions, the remaining components of the parasitic series resistance can be greatly reduced, resulting in an increased maximum frequency of oscillation, f_max. AlAs/GaAs Schottky-collector RTDs were fabricated using 0.1 μm T-gate technology developed for high electron mobility transistors. From their measured dc and microwave parameters, and including the effect of the quantum well lifetime, f_max=900 GHz is computed     

Germanium-diffused waveguides in silicon for λ=1.3 μm andλ=1.55 μm with losses below 0.5 dB/cm

The authors present a simple technique for the fabrication of integrated optical channel waveguides that are prepared by indiffusion of an E-beam evaporated amorphous alloy of germanium and silicon into commercially available silicon with low dopant concentration, using only simple technological processes such as standard lithography, PVD, and diffusion. The waveguides are polarization independent and have waveguide losses as low as 0.3 dB/cm at wavelengths of λ=1.3 μm and λ=1.55 μm. The spot sizes are well suited for low-loss single-mode fiber device coupling, being on the order of a few microns in both horizontal and vertical directions     

Characteristics of GaAsSb single-quantum-well-lasers emitting near1.3 μm

We report data on GaAsSb single-quantum-well lasers grown on GaAs substrates. Room temperature pulsed emission at 1.275 μm in a 1250-μm-long device has been observed. Minimum threshold current densities of 535 A/cm² were measured in 2000-μm-long lasers. We also measured internal losses of 2-5 cm^-1, internal quantum efficiencies of 30%-38% and characteristic temperatures T₀ of 67°C-77°C. From these parameters, a gain constant G₀ of 1660 cm^-1 and a transparency current density J_tr of 134 A/cm² were calculated. The results indicate the potential for fabricating 1.3-μm vertical-cavity surface-emitting lasers from these materials     

New III-V double-heterojunction laser emitting near 3.2 μm

Double heterostructure lasers based on the InAsSbP/InAsSb system have been prepared by liquid phase epitaxy. They operate at 78 K near 3.2 μm, with a threshold current density of 4.5 kA/cm² in pulsed conditions. The characteristic temperature T₀ is 30 K     

High performance 0.1 μm dynamic threshold MOSFET using indiumchannel implantation

In this letter, we demonstrate a high-performance 0.1 μm dynamic threshold voltage MOSFET (DTMOS) for ultra-low-voltage (i.e., <0.7 V) operations. Devices are realized by using super-steep-retrograde indium-channel profile. The steep indium-implanted-channel DTMOS can achieve a large body-effect-factor and a low V_th simultaneously, which results in an excellent performance for the indium-implanted DTMOS     

Sub-0.1 μm NMOS transistors fabricated using laser-plasmapoint-source X-ray lithography

We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 μm with an effective channel length of 0.075 μm. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography     

Best structures for deep submicrometer (0.1-0.3 μm) MOS devices

Summary form only given. The LDD-type structure has begun to encounter difficulties in satisfying transistor requirements in manufacturing due to a basic conflict between the need to have a graded drain profile for hot carrier suppression and the requirements for manufacturability and performance which place emphasis on a shallow, steeply profiled drain. One approach for overcoming this conflict and limitation is a MOS transistor structure called the hot-carrier suppressed (HCS) MOSFET. In this approach, a lower doped drain region is placed behind, or above, the shallow, heavier doped drain region rather than being placed adjacent to the channel region. This structure is described in detail, and its simulated performance compared with that of the LDD and conventional MOSFET structures     

The correlation between gate current and substrate current in 0.1μm NMOSFET's

The correlation between gate and substrate currents in NMOSFET's with effective channel length, L_eff, down to 0.1 μm is investigated within the general framework of the lucky-electron model. It Is found that the correlation coefficient, Φb/Φ_i, decreases with decreasing L_eff in the 0.1 μm regime, where Φ_b is the effective Si-SiO₂ barrier height for channel hot-electrons, and Φ_i is the effective threshold potential for impact ionization. Furthermore, this effect becomes stronger in NMOSFET's with shorter L_eff. These experimental results suggest the need for further investigation on specific assumptions in the lucky-electron model to understand hot-electron behavior and impact ionization-mechanisms in 0.1 μm-scale NMOSFET's     

A novel 0.1 μm MOSFET structure with inverted sidewall andrecessed channel

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 μm, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V_D=2 V is 446 mS/mm for the 0.1 μm n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 μm to 0.1 μm and good subthreshold characteristics are achieved for 0.1 μm channel device     

High-performance, 0.1 μm InAlAs/InGaAs high electron mobilitytransistors on GaAs

This letter describes the material characterization and device test of InAlAs/InGaAs high electron mobility transistors (HEMTs) grown on GaAs substrates with indium compositions and performance comparable to InP-based devices. This technology demonstrates the potential for lowered production cost of very high performance devices. The transistors were fabricated from material with room temperature channel electron mobilities and carrier concentrations of μ=10000 cm² /Vs, n=3.2×10¹² cm^-2 (In=53%) and μ=11800 cm²/Vs, n=2.8×10¹² cm^-2 (In=60%). A series of In=53%, 0.1×100 μm² and 0.1×50 μm² devices demonstrated extrinsic transconductance values greater than 1 S/mm with the best device reaching 1.074 S/mm. High-frequency testing of 0.1×50 μm² discrete HEMT's up to 40 GHz and fitting of a small signal equivalent circuit yielded an intrinsic transconductance (g_m,i) of 1.67 S/mm, with unity current gain frequency (f_T) of 150 GHz and a maximum frequency of oscillation (f_max) of 330 GHz. Transistors with In=60% exhibited an extrinsic g_m of 1.7 S/mm, which is the highest reported value for a GaAs based device     

InAs quantum-dot lasers operating near 1.3 μm with highcharacteristic temperature for continuous-wave operation

A high characteristic temperature with T₀ of 126 K under continuous-wave operation is obtained for an InAs/GaAs quantum dot laser. A triple-stacked active region with an energy separation of 95 meV between the ground and first excited radiative transitions is used to achieve a ground state saturation gain at 300 K of 13 cm^-1, and high internal quantum efficiency of 74%     

Counter doping into uniformly and heavily doped channel region ofsub-0.1 μm SOI MOSFETs

We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V_th and to eliminate parasitic edge or back gate transistors. We derived a model for V_th as a function of the projected range, Rp and dose, Φ_D, of the counter doping, and showed that V_th is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V_th roll-off free 0.075 μm-L_Geff nMOSFET with low off-state current