A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.     

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

Polarization independent bulk active region semiconductor optical amplifiers for 1.3 /spl mu/m wavelengths

Semiconductor optical amplifiers for 1.3 /spl mu/m are realized combining single-step grown bulk InGaAsP active region with ridge-waveguides. Achieved fiber-to-fiber gains are in excess of 27 dB with spectral ripples below 0.2 dB. Gain is polarization insensitive to within 1 dB over the entire range of driving current, 1.28 /spl mu/m to 1.34 /spl mu/m wavelength and 10/spl deg/C to 50/spl deg/C heat sink temperature. Intrinsic noise figure is 6.3 dB. Gain saturates at +10 dBm.     

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

A decoupling circuit using an operational amplifier is proposed to suppress substrate crosstalk in mixed-signal system-on-chip (SoC) devices. It overcomes the parasitic inductance problem of on-chip capacitor decoupling. The effect of the proposed decoupling circuit is not limited by parasitic fine impedance. A 0.13-/spl mu/m CMOS test chip showed that substrate noise at frequencies from 40 MHz to 1 GHz was incrementally suppressed by sequentially activating three of the proposed circuits in parallel. The power dissipation of each circuit was 3.3 mW at a 1.0-V power supply. The test chip measurement showed that the proposed decoupling reduced crosstalk by 31% at 200 MHz, whereas it was reduced by 4.4% with capacitor decoupling. This 7:1 ratio, or 17 dB, corresponds to the gain of the opamp. Design of the opamp and its feedback loop for active decoupling is simple, making the opamp useful for SoC applications.     

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

Efficient PDFA module using high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber

The highest reported single-pass gain coefficient of 0.36 dB/mW has been achieved using a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber, with a /spl Delta/n of 6.6%, a core diameter of 1.2 /spl mu/m and a transmission loss of 250 dB/km at 1.2 /spl mu/m. This fiber was used to construct an efficient PDFA module with a MOPA-LD. A small-signal net gain of 22.5 dB was achieved at 1.30 /spl mu/m with a pump power of 23m mW.     

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-/spl mu/m CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm/sup 2/.     

Germania-based core optical fibers

Germania-glass-based core silica glass cladding single-mode fibers (/spl Delta/n up to 0.143) with a minimum loss of 20 dB/km at 1.9 /spl mu/m were fabricated by the modified chemical vapor deposition (MCVD) method. The fibers exhibit strong photorefractivity with the type-IIa-induced refractive-index modulation of 2/spl times/10/sup -3/. The Raman gain of 300 to 59 dB/(km/spl middot/W) was determined at 1.07 to 1.6 /spl mu/m, respectively, in a 75 mol.% GeO/sub 2/ core fiber. Only 3 m of such fibers are enough for the creation of a 10-W Raman laser at 1.12 /spl mu/m with a 13-W pump at 1.07 /spl mu/m. Raman generation in optical fiber at a wavelength of 2.2 /spl mu/m was obtained for the first time.     

35-dB gain Tm-doped ZBLYAN fiber amplifier operating at 1.65 /spl mu/m

We demonstrate the first high gain rare-earth-doped fiber amplifier operating at 1.65 /spl mu/m. It consists of ZBLYAN fiber with a Tm/sup 3+/-doped core and Tb/sup 3+/-doped cladding, pumped by 1.22 /spl mu/m laser diodes. It is possible to achieve efficient amplification with Tm/sup 3+/ ions if their amplified spontaneous emission (ASE) in the 1.75 to 2.0 /spl mu/m wavelength region is suppressed by doping Tb/sup 3+/ ions in the cladding. A two-stage-type fiber amplifier is constructed and a signal gain of 35 dB is achieved for a pump power of 140 mW. A gain over 25 dB is realized in the 1.65 /spl mu/m to 1.67 /spl mu/m wavelength region.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

Low-loss InGaAsP/InP submicron optical waveguides fabricated by ICP etching

The fabrication and characterisation of low-loss InGaAsP/InP optical submicron waveguides made with ICP etching is reported. Their width ranges from 0.2 to 2 /spl mu/m. For the 0.5 /spl mu/m width, the propagation losses at /spl lambda/=1.55 /spl mu/m as low as 4.2 dB/mm have been measured.     

Gain-flattened Er/sup 3+/-doped fiber amplifier for a WDM signal in the 1.57-1.60-/spl mu/m wavelength region

A gain-flattened Er/sup 3+/-doped silica-based fiber amplifier (EDFA) has been constructed for a 1.58-/spl mu/m band WDM signal. This EDFA exhibits uniform amplification characteristics with a gain excursion of 0.9 dB for a four-channel WDM signal in the 1.57-1.60 /spl mu/m wavelength region. The average signal gain and the noise figure for the WDM signal are 29.5 dB and less than 6.3 dB, respectively. The use of this EDFA in parallel with a 1.55-/spl mu/m band EDFA will expand the WDM transmission wavelength region.     

The universal opamp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition

A versatile analog building block denoted the universal operational amplifier (opamp) is introduced. The circuit is a generalized version of the fully differential difference opamp with 2n weighted differential inputs. Applications in resistorless and capacitorless continuous-time linear weighted voltage addition are discussed. Experimental results of a test chip prototype are shown that validate the proposed approach. Simulations show potential for high frequency operation of the circuit with gain-bandwidth close to 140 MHz in 0.5-/spl mu/m CMOS technology.     

Self-tuning algorithms for high-performance bandpass switched-capacitor /spl Sigma//spl Delta/ modulators

Switched-capacitor high-frequency bandpass /spl Sigma//spl Delta/ modulators could suffer from capacitor mismatch, finite opamp dc gain, and finite opamp bandwidth. These problems make the notch frequency and the quality factor of the zeros of the noise transfer function to deviate from their nominal values, strongly affecting the modulator dynamic range (DR). In order to avoid this situation, two sampled-data algorithms have been developed which allow to self-calibrate the bandpass /spl Sigma//spl Delta/ modulators. They use 3500 gate and 0.043 mm/sup 2/ area and consume power only when they are active, while, when the system is on, they are off and do not interfere with standard operation. The validity of the proposal is demonstrated by a silicon prototype in which the proposed solution allows to guarantee a 75-dB DR performance also under worst case conditions. In the particular case, it allows for the recovery of 3 dB in the SNR for the 200-kHz FM band (from 73 to 76 dB).     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

Very large effective area singlemode photonic bandgap fibre

A photonic bandgap fibre consisting of a 34 /spl mu/m diameter pure silica core surrounded by a periodic cladding has been modelled and characterised. It guides a robust HE/sub 11/ mode at 1.55 /spl mu/m with a 517 /spl mu/m/sup 2/ effective area and 0.4 dB/m propagation losses.