A Facile In Situ Surface-Functionalization Approach to Scalable Laminated High-Temperature Polymer Dielectrics with Ultrahigh Capacitive Performance

High-temperature dielectric materials for capacitive energy storage are in urgent demand for modern power electronic and electrical systems. However, the drastically degraded energy storage capabilities owing to the inevitable conduction loss severely limit the utility of dielectric polymers at elevated temperatures. Herein, a new approach based on the in situ preparation of oxides onto polyimide (PI) films to high-temperature laminated polymer dielectrics is described. As confirmed by computational simulations, the charge injection at the electrode/dielectric interface and electrical conduction in dielectric films are substantially depressed via engineering the in situ prepared oxide layer in the laminated composites. Consequently, ultrahigh dielectric energy densities and high efficiencies are simultaneously achieved at elevated temperatures. Especially, an excellent energy density of 1.59 J cm⁻³ at a charge–discharge efficiency of above 90% has been achieved at 200 °C, outperforming the current dielectric polymers and composites. Together with its excellent discharging capability and cyclic reliability, the laminate-structured film is demonstrated to be a promising class of polymer dielectrics for high-power energy storage capacitors operating at elevated temperatures. The facile preparation method reported herein is readily adaptable to a variety of polymer thin films for energy applications under extreme environments.     

Optimization of Epoxy-Barium Titanate Nanocomposites for High Performance Embedded Capacitor Components

One of the most promising avenues to meet the requirements of higher performance, lower cost, and smaller size in electronic systems is the embedded capacitor technology. Polymer-ceramic nanocomposites can combine the low cost, low temperature processability of polymers with the desirable electrical and dielectric properties of ceramic fillers, and have been identified as the major dielectric materials for embedded capacitors. However, the demanding requirements of mechanical properties and reliability of embedded capacitor components restrict the maximum applicable filler loading (<50vol%) of nanocomposites and thereby limit their highest dielectric constants (<50) for real applications. In this paper, we present a study on the optimization of the epoxy-barium titanate nanocomposites in order to obtain high performance, reliable embedded capacitor components. To improve the reliability of polymer-ceramic nanocomposites at a high filler loading, the epoxy matrix was modified with a secondary rubberized epoxy, which formed isolated flexible domains (island) in the continuous primary epoxy phase (sea). The effects of sea-island structure on the thermal mechanical properties, adhesion, and thermal stress reliability of embedded capacitors were systematically evaluated. The optimized, rubberized nanocomposite formulations had a high dielectric constant above 50 and successfully passed the stringent thermal stress reliability test. A high breakdown voltage of 89MV/m and a low leakage current of about 1.9times10^-11A/cm² were measured in the large area thin film capacitors     

Review of Polymer‐Based Nanodielectric Exploration and Film Scale‐Up for Advanced Capacitors

The uprising demands for electrical power and electrification requires advanced dielectric functionalities including high capacitance density, high energy density, high current handling capability, high voltage, high temperature, high thermal conductivity, light weight, and environmental reliability. Nanodielectric engineering emerges and attracts extensive efforts from many countries as a result. Unlike prior reviews focusing on lab scale nanocomposite study, this review focuses on recent innovations in polymer‐based nanodielectric design on a large scale and their film scale‐up efforts for advanced capacitors. The unconventional polymer‐nanofiller engineering and their process in the last two decades are discussed. The nanofunctionalized polymers on a molecular level for high dielectric constants and high dielectric strength are briefly described. The challenge associated with film scale‐up and retention of nanodielectric properties are then pointed out to be crucial toward a transfer of dielectric and capacitor technology. Several important attempts at scaling up dielectric films and capacitors recently supported by the US government and industry are reviewed. An alternative strategic approach to achieving high performance polymer films is introduced by leveraging 2D surface coating on commercially mature large‐scale polymer films. Future pathways for high quality scalable dielectric films exhibiting desirable dielectric properties and feasibility for capacitor manufacturing are suggested.     

0.18μm Low—k SiOF Integration and Reliability

The requirement of reduced RC delay and cross-talk for multilevel interconnect ULSI applications has enthusiastically driven process development for seeking suitable low dielectric constant materials with sufficient k value.The replacement of HDP FSG(k-3.5-3.6)with conventional SiO2 as a manufacturable intermetal dielectric layer(IMD) has achieved 0.18μm ULSI interconnect technology.The electrical test result,via resislance as well as multilevel CMOS transistor characteristics (such as plasma damage,device degradation,hot carrier,etc.)are basically compatible to those conventional oxide as IMD.Assessment of metal line-to-line capacitance reduction using comb capacitors yields values of reduction range 10%-14% comparing FSG to convention oxide.The effectiveness of low-k FSG in circuit performance is also demonstrated.Comparisons of ring-oscillator speed performance for metal runners with various width and space show speed improvement approximately 10% for the FSG.Impact of FSG on reliability is evaluated and results show manufacturing compatibility to conventional SiO2.     

Topological‐Structure Modulated Polymer Nanocomposites Exhibiting Highly Enhanced Dielectric Strength and Energy Density

Dielectric materials with high electric energy densities and low dielectric losses are of critical importance in a number of applications in modern electronic and electrical power systems. An organic–inorganic 0–3 nanocomposite, in which nanoparticles (0‐dimensional) are embedded in a 3‐dimensionally connected polymer matrix, has the potential to combine the high breakdown strength and low dielectric loss of the polymer with the high dielectric constant of the ceramic fillers, representing a promising approach to realize high energy densities. However, one significant drawback of the composites explored up to now is that the increased dielectric constant of the composites is at the expense of the breakdown strength, limiting the energy density and dielectric reliability. In this study, by expanding the traditional 0–3 nanocomposite approach to a multilayered structure which combines the complementary properties of the constituent layers, one can realize both greater dielectric displacement and a higher breakdown field than that of the polymer matrix. In a typical 3‐layer structure, for example, a central nanocomposite layer of higher breakdown strength is introduced to substantially improve the overall breakdown strength of the multilayer‐structured composite film, and the outer composite layers filled with large amount of high dielectric constant nanofillers can then be polarized up to higher electric fields, hence enhancing the electric displacement. As a result, the topological‐structure modulated nanocomposites, with an optimally tailored nanomorphology and composite structure, yield a discharged energy density of 10 J/cm³ with a dielectric breakdown strength of 450 kV mm^–1, much higher than those reported from all earlier studies of nanocomposites.     

Environmental Qualification Testing and Failure Analysis of Embedded Resistors

Embedding passive components (capacitors, resistors, and inductors) within printed wiring boards (PWBs) is one of a series of technology advances enabling performance increases, size and weight reductions, and potentially economic advantages in electronic systems. This paper explores the reliability testing and subsequent failure analysis for laser-trimmed Gould subtractive nickel chromium and MacDermid additive nickel phosphorous embedded resistor technologies within a PWB. Laser-trimmed resistors that have been “reworked” using an inkjet printing process to add material to their surface to reduce resistance have also been considered. Environmental qualification testing performed included: thermal characterization, stabilization bake, temperature cycling, thermal shock and temperature/humidity aging. In addition, a pre/post-lamination analysis was performed to determine the effects of the board manufacturing process on the embedded resistors. A failure analysis consisting of optical inspection, scanning acoustic microscope (SAM) and environmental scanning electron microscope (ESEM) imaging, and PWB cross-sectioning was employed to determine failure mechanisms. All the embedded resistors were trimmed and the test samples included resistors fabricated both parallel and perpendicular to the weave of the board dielectric material. Material stability assessment and a comparison with discrete resistor technologies was performed.     

Novel polymer-ceramic nanocomposite based on new concepts for embedded capacitor application (I)

A rapid growth of mixed-signal integrated circuits is driving the needs of multifunction and miniaturization of the component in electronics applications. Polymer-ceramic composites have been of great interest as embedded capacitor materials because they enabled companies to combine the processability of polymers with the high dielectric constant of ceramics. This paper presents the preparations and performance characterizations of novel polymer-ceramic nanocomposites based on new concepts for embedded capacitor application. First, metal particle nickel-filled nanocomposite with high dielectric constant was evaluated as a candidate for embedded capacitors. Two types of nickel particles were selected with the size of 400 and 150nm, respectively. With proper filler loading and highly dispersed, a high dielectric constant of over 90 was observed with a filler loading ratio of 60-vol%. Second, the surface modification of a barium titanate (BTO) particle was also attempted in nanocomposite. Phthalocyanine-coated BTO (Pc-coated BTO) was selected as filler to prepare the composite. Its dielectric constant was observed as over 80 at 1MHz, which was much higher than that of composite derived from commercial BTO. Last, in order to improve the processability of the nanocomposite, 4, 4'-diphenylmethane bismaleimide (BMI) was selected as a matrix polymer by the combination with polyamide (PA). Higher dielectric constant nanocomposite derived from PA/BMI and Pc-coat BTO was obtained, and its potential application towards embedded capacitors was also evaluated.     

高导热聚合物基复合封装材料及其应用

微电子封装密度的提高对传统环氧塑封料的导热性能提出了更高的要求,将高导热的陶瓷颗粒/纤维材料添加到聚合物塑封材料中可获得导热性能好的复合型电子封装材料。文章结合高导热环氧塑封材料的研究工作,评述了高热导聚合物基复合封装材料的材料体系、性能特点和在微电子封装中的应用情况。分析讨论了影响聚合物基复合电子封装材料导热性能和介电性能的因素,提出了进一步提高聚合物基复合电子封装材料导热性能的途径。     

Qualification procedure for moisture in embedded capacitors

Embedding passives in PCB permits to gain in integration density while enhancing electromagnetic compatibility performances. The choice of the dielectric film is fundamental for large frequency band stability of embedded capacitances. However, these materials are prone to water absorption, which can lead to functional parameter degradations and additional stresses at the interfaces. This paper presents experimental capacitors embedded in FR-4, and finite element simulations of moisture absorption in various dielectric materials. Technological choices, as well as the qualification procedure, can be improved thanks to the simulation results.     

Effect of the polymer matrices on the dielectric behavior of a percolative high-k polymer composite for embedded capacitor applications

High dielectric constant (high-k) polymer composites are of great interest for embedded capacitor applications. Previously, we demonstrated that epoxy—aluminum composites are promising for embedded capacitor applications, because they have a high dielectric constant and a low dielectric loss due to the core—shell structure of the self-passivated aluminum particles. In this work, to further understand the dielectric behavior of aluminum composites, lower-loss polymers such as silicone, polyimide, polynorbornene, and benzocyclobutene were explored as matrices for the aluminum composites. It is found that the polymer matrices can significantly change the dielectric properties of the aluminum composites. A polymer matrix with a lower dielectric constant generally results in a lower dielectric constant of its aluminum composites. In this regard, polymer—aluminum composites have a similar dielectric characteristic as polymer—ceramic composites. Thermomechanical properties of aluminum composites were characterized by a thermomechanical analyzer.     

High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

Integrated capacitors for conductive lithographic film circuits

This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed electrode films. Multilayer circuit boards with printed components and interconnect can be fabricated using this technique     

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Metal–insulator–metal capacitor (MIMC) reliability and electrical properties are defined by the TDDB lifetime, breakdown voltage and leakage current. In this article, the correlation is determined between these electrical properties and the physical and chemical properties of the SiN dielectric layer. It is demonstrated how a SiN dielectrics with a high refractive index have high Si content and show an increased initial leakage current. However, contradictory to the high leakage current, these dielectrics also show high lifetimes. It is shown that SiN dielectrics with a high Si content contain high numbers of charge trapping centers. Over time, a high concentration of trapped charges is build up to such an extend that the local electric field over the dielectric is significantly decreased. This results in the observed reliability improvement of the dielectric. The final intrinsic quality and reliability of MIMC capacitors can therefore be determined by measurable physical properties of the MIMC dielectric at the time of the deposition of this layer.     

Preparation and Dielectric Characteristics of Semitransparent CoFe2O4–P(VDF-TrFE) Nanocomposite Films

Polymer–ceramic nanocomposites play an important role in embedded capacitors. However, polymer–ceramic dielectrics are limited for commercial applications due to their low transmittance, poor adhesion, and poor thermal stress reliability at high filler loadings. Thus, materials design and processing is critical to prepare films with improved dielectric properties and low filler loading. In this work, we use a spin coating-assisted method to fabricate poly(vinylidene fluoride-co-trifluoroethylene) [P(VDF-TrFE)]–CoFe₂O₄ (CFO) nanocomposite films. Magnetic CFO nanoparticles in the size range of 10 nm to 40 nm were successfully synthesized using a hydrothermal process. The dispersion of the nanoparticles, the dielectric properties, and the transmittance of the nanocomposite films were studied. The dielectric constant of the nanocomposite films increased by about 45% over the frequency range of 100 Hz to 1 MHz, compared with that of pristine P(VDF-TrFE) film. Optical measurements indicated that the transmittance of the films remains above 60% in the visible range, indicating a relatively low content of CFO in the polymer matrix. Our experimental results suggest that spin coating-assisted dispersion may be a promising route to fabricate dielectric polymer–ceramic nanocomposite films of controllable thickness.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Modeling ceramic filled polymer integrated capacitor formationusing neural networks

Integrated decoupling capacitors for MCM-L/D technology are an important component for next-generation electronic packaging applications. This paper presents a statistically designed experiment for systematic characterization of the dielectric constant and loss tangent of integrated capacitors formed by mixing lead magnesium niobate (PMN) particles into polyimide and benzocyclobutene (BCB) polymer dielectric layers. We determine these quantities as a function of the type of polymer material, a volume fraction of ceramic in the polymer matrix, a polymer cure time, and polymer cure temperature. These factors have been examined by means of a D-optimal experiment. Results indicate manipulation of each of the four factors over the ranges examined lead to considerable variation in dielectric constant and loss tangent. Based on data from these experiments, we train neural networks to model this process variation as a function of above variables. Using this methodology, we determine proper combinations of polymer/ceramic materials and processing conditions to achieve desirable electrical properties     

Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates

Understanding and quantifying the RLC characteristics of the embedded passives under thermomechanical deformation during fabrication and accelerated thermal conditions is necessary for their successful implementation. Embedded passives are composite layers with dissimilar material properties compared to the neighboring layers in the integral substrate. The ongoing project explores the fabrication, multifield physics-based reliability modeling and accelerated testing of embedded passive test vehicles. As a first step, in this paper, the effect of thermomechanical deformation on the electrical characteristics of embedded capacitors is studied at frequencies from 100 KHz to 2 GHz using two test vehicles. Test vehicles with embedded passives were fabricated and were subjected to accelerated thermal cycles between -55degC to 125degC, between -40degC to 125degC and high humidity and temperature conditions of 85degC/85% RH. Significant changes in the electrical parameters of the embedded capacitors are observed. The fabrication process mechanics with multiphysics global-local modeling methodology is demonstrated to study the effect of thermal cycling on the electrical characteristics of embedded capacitors. The results obtained from the multiphysics global-local modeling methodology are validated against the measured electrical characteristics of the fabricated functional test boards. The effect of changes in electrical parameters of embedded passives on system performance of low-pass filters is presented     

Impact of the surface roughness on the electrical capacitance

A new hybrid approach consists to use the advantages of both systems namely the high geometric aspects of the electrodes of the ultracapacitor and the high dielectric strength of polymer materials used in dielectric capacitors. The surface roughness of the electrodes of the ultracapacitor is manufactured with nano-porous materials; activated carbon and carbon nanotubes (CNTs).Many compositions of both carbonaceous materials are tested with different insulating materials (liquid and solid) to constitute the hybrid capacitor. It appears that the capacitance increases with the carbonaceous composition: An increasing from 15 to 40% is observed as compared to a plane capacitor, it can be twice with a 100 wt% of CNTs content. But, the impregnation of the insulating material in the surface roughness remains the key point of the realization of the hybrid capacitor. The roughness accessibility is a major property to optimize in order to improve the impregnation of the insulating material to increase the electrical capacitance.     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Reliability of gate dielectrics and metal–insulator–metal capacitors

In this review paper reliability characterisation methods of SiO₂ as gate dielectric and metal–insulator–metal capacitors with various dielectrics are discussed. It includes the test structure design, the stress and measurement sequences, the raw data analysis and the extrapolation models of measured time to breakdown to lifetimes at operating conditions and targeted product failure rates. For each topic various references are given where further details are described. Especially pitfalls of approaches and problem areas are highlighted.