Novel dynamic c.m.o.s. amplifier for switched-capacitor integrators

A novel dynamic c.m.o.s. amplifier for switched-capacitor integrators is described. The amplifier does not consume any static power and requires a very small chip area.     

A New Balanced CMOS Controlled Integrator for Ultra High Frequency Applications

New implementations for single ended and balanced integrators using translinear mixed cells and operating in voltage mode are described. These integrators use the input translinear cell of a CMOS current controlled conveyor. The frequency ranges of correct operation of the compensated integrator are analyzed. It is shown that the high cut-off frequency now becomes located to the higher possible values. These integrators are designed and simulated using a 0.8 μ m CMOS process. The frequency ranges of right operation of the compensated and uncompensated integrators are compared. They confirm very well the theory and underline the efficiency of the compensation methods.     

A Nonlinear Noise-Shaping Delta-Sigma Modulator with On-Chip Reinforcement Learning*

The stability and quality of noise shaping is a concern in the design of higher-order delta-sigma modulators for oversampled analog-to-digital conversion. We reformulate noise-shaping modulation alternatively as a nonlinear control problem, where the objective is to find the binary modulation sequence that minimizes signal swing in a cascade of integrators operating on the difference between the input signal and the modulation sequence. Reinforcement learning is used to adaptively optimize a nonlinear neural classifier, which outputs modulation bits from the values of the input signal and integration state variables. Analogous to the pole balancing control problem, a punishment signal triggers learning whenever any of the integrators saturate. Experimental results obtained from a VLSI modulator with integrated classifier, trained to produce stable noise shaping modulation of orders one and two, are presented. The classifier contains an array of 64 locally tuned, binary address-encoded neurons and is trained on-chip with a variant on reinforcement learning.     

A novel SFG structure for C-T high-pass filters

A signal flow graph (SFG) structure for simulating passive high-pass ladder filters, called the incremental integration structure, is proposed. The structure requires the use of integrators with nonintegrating inputs, and an implementation based on the MOSFET-C technique is discussed. The incremental integration structure is compared to the leapfrog and direct SFG simulation structures. Leapfrog high-pass filters are relatively simple and show good noise properties, but they are based on differentiators and thus stability problems exist. The direct SFG simulation method is based on integrators and has good stability properties, but it leads to a relatively high circuit complexity and a high noise level. However, the incremental integration structure inherits the low-noise properties of the leapfrog structure and the good stability of the direct SFG simulation method. A sixth-order elliptic high-pass filter chip with a passband frequency of 3.0 kHz has been manufactured, and measurements support the validity of the approach     

Topology-independent predistortion for integrator-based filters

This paper proposes a topology-independent predistortion for filters using integrators. This employs integrators having the same structure, the same-value elements and an electrically controllable unity-gain frequency and compensates for the deviation of frequency characteristics due to excess phase shifts of integrators without knowledge of a filter topology. The effectiveness of the proposed method is demonstrated through SPICE simulations.     

A reduced capacitor spread algorithm for elliptic bandpass SC filters

A modification of a well-known algorithm for simulating elliptic LC ladder filters by switched-capacitor (SC) technique is presented, The filter terminations were realized without damped integrators. The modification was proven useful in reducing the capacitance spread and total capacitance in high-Q bandpass SC filters: improvements by factors of five and six were obtained in the design of sixth- and tenth-order bandpass filters, respectively. A chip, including four sixth-order bandpass filters in the audio range, was designed and found to function properly.     

Using New Hybrid Integrators to Design IIR Fractional-Order Integrators via Impulse Invariance Method

This paper presents a method for designing fullband and non-fullband IIR digital integrators with linear phase that has been used to approximate fractional-order integrators with IIR filters. Several numerical integration rules have been considered in this study, namely, Euler, Simpson, Schneider, bilinear, and F₀₁₂. The main idea in our design is based on interpolating the well-known integration rules (Euler, Bilinear and Simpson) proposed by Al-Alaoui combined with deterministic signal modeling techniques. Numerical examples are presented to illustrate the performance of the proposed integrators. It was found that the Euler–Simpson integrator gives better approximation accuracy than existing integrators.     

New improved fractional order integrators using PSO optimisation

This article investigates the optimal results of new improved fractional order integrators (FOIs) of different orders. Mathematical models of FOIs have been first developed by a single-step procedure of direct linear interpolation of fractional integrators based on Al-Alaoui operator in fractional domain itself, instead of using three steps of the well-known conventional method, namely, digital interpolation, series expansion and truncation. Later, these transfer functions (TFs) are optimised for their coefficient values for finding a minimum error function by particle swarm optimisation (PSO) algorithm. Simulation results of magnitude responses, phase responses and relative magnitude errors (dB) for all the proposed half integrators have validated the effectiveness of this new technique of interpolation of fractional order operators, mixed with PSO algorithm. A parallel comparison has been also drawn between the proposed optimised half integrators and those obtained by discretisation of PSO optimised integer order digital integrators (DIs) to properly support the proposed novel combination of interpolation and PSO, both applied together in fractional domain.     

Switched-capacitor FSK modulator and demodulator in CMOS technology

A switched-capacitor FSK modulator/demodulator built in silicon-gate CMOS technology is described. The modulator is based on a programmable harmonic oscillator using two stray-insensitive integrators. The centerpiece of the FSK demodulator is a switched-capacitor voltage-controlled oscillator. A simple post-detection processor restores the digital data. Both circuits have been designed for the 600-baud modem channel with 1500 Hz center frequency and /spl plusmn/200 Hz frequency shifts, but the demodulator operates in the 1200-baud channel as well. Due to dynamic biasing the operational amplifiers feature high slew rate, high voltage gain, and low power for capacitive loads.     

A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques

This paper presents a new structure for high-resolution, low-power and wideband discrete time multi-stage (DT-MASH) sigma-delta (ΣΔ) modulators. It uses multi-bit digital input feed forward path (DFF) and noise coupling (NC) techniques. With the DFF technique, the modulator does not need a power-consuming analog adder at the quantizer input, and the number of comparators of the quantizer will be reduced significantly. Also, because of the reduced swing of the modulator’s integrators, low power integrators can be used. Using a second-order NC technique with no extra active block, the order of the modulator, which uses some paths between analog stages, is increased, and its performance is improved with zero-optimization of the modulator’s noise transfer function (NTF). Behavioral simulations and extensive mathematical analyses confirm the effectiveness of the proposed structure. The effect of the non-idealities in the DFF and NC paths were considered in the behavioral simulations. To examine its performance, a MASH 2–1 modulator was designed in the circuit level with a 180-nm CMOS technology and 1.8 V power supply. The integrators use a new op-amp switching technique to reduce total power consumption. With an over-sampling ratio (OSR) of 8 for the 10 MHz signal bandwidth, the proposed structure improves the signal-to-noise and distortion ratio (SNDR) by 28 dB compared with a conventional MASH 2–1 structure at approximately the same power consumption and very low complexity.

     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

差分式CMOS连续时间电流模式滤波器

提出了基地电流镜电路的差分式连续时间电流模式积分器，并用此积分器构成了全差分式连续时间电流模式低通及带通滤波器，分析并模拟了所提出的积分器及滤波器的特性，结果表明所提出了电路的具有结构简单，对称性好，失真小等优点，适于全集成。     

Time-constant control of microwave integrators using transmission lines

A model describing the time constant of a transmission-line integrator is presented. By representing the formulations of integrators in the discrete-time (or Z) domain, we implement the integrators with equal-length transmission lines. Three integrators with different time constants and frequency bands are built and tested. The experimental results are in good agreement with theoretical values.     

A feedforward excess-phase cancellation technique for integrators

Integrators are useful analogue function blocks. A representative application of integrators is a continuous-time filter on an integrated circuit. Excess phase shift of integrators is one of the most severe problems, because excess phase shift at the unity gain frequency degrades the frequency characteristics of the filters. This paper describes a feedforward excess-phase cancellation technique. The proposed technique is applied to integrators which have feedback with an amplifier. The proposed idea is verified by experiment. It is shown that the excess-phase shift due to the gain-bandwidth product of operational amplifiers is cancelled. The proposed technique is useful for realization of integrated continuous-time filters using integrators because extra capacitors are unnecessary. An integrator with the excess-phase cancellation and a third-order leapfrog filter using the integrator are designed and demonstrated by HSPICE simulation. The integrator has a parasitic pole whose frequency is proportional to the unity gain frequency. The simulation results show that the phase characteristics are improved by the proposed technique over the wide range of the unity gain frequency.     

Instantaneous Companding Current-Mode Oscillator Based on Class AB Transconductor

A family of DC stable electronically tunable instantaneous companding integrators are presented. Based on these integrators, an electronically tunable oscillator is proposed. Since theoretically the integrators used in the proposed oscillator are inherently linear, they are capable of producing oscillating current signals with low THD levels.     

High frequency stability of near-perfect active phase compensated integrators

An investigation carried out on high frequency stability of near-perfect active phase compensated noninverting and inverting integrators is presented. The necessary and sufficient conditions to operate these integrators in a stable mode are derived.     

Realisation of 2D analogue filters

A modified method is presented for the realisation of 2D analogue filters used for processing television images. The proposed procedure reduces the required number of integrators considerably. For Example, for the second- and third-order cases, the reduction in the number of integrators would be seven and 21, respectively.<>     

偶数阶电流模椭圆滤波器的综合设计

本文提出了一种基于MOCCII的任意偶数阶电流模椭圆滤波器综合设计方法。通过对n阶(偶数)椭圆传输函数进行分析,将其分解成一系列能用无损积分器实现的表达式;并对输出电流信号进行线性组合,以实现了偶数阶的电流模式椭圆滤波器的综合。该方法实现的电路结构简单,所用有源和无源元件最少,仅由n个接地电容,(3n-1)/2个有源器件和接地电阻构成。给出了四阶高通、低通和带通椭圆形滤波器的设计实例。Pspice仿真结果表明采用该方法设计偶数阶电流模式椭圆滤波器是可行的,适用的。     

Reducing the effect of charge-transfer inefficiency in a c.c.d. video integrator

The usefulness of c.c.d.s as video integrators is limited by the charge-transfer inefficiency of the device. A method of coding the signal before passage through the c.c.d. is described which greatly reduces the effect of this inefficiency.     

Some considerations of signal/noise improvement using recursive and nonrecursive integrators

The letter compares the signal-to-noise improvement attainable with recursive and nonrecursive integrators as a function of the number of sample records available and the effective summing capability of the integrators. The conditions under which one or other integrator gives the better performance are established.