Efficient network folding techniques for routing permutations inVLSI

Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M相似文献   

A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture

A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).     

Complexity of gradient projection method for optimal routing indata networks

In this paper, we derive a time-complexity bound for the gradient projection method for optimal routing in data networks. This result shows that the gradient projection algorithm of Goldstein-Levitin-Poljak type formulated by Bertsekas (1982), Bertsekas and Gallager (1987) and Bertsekas et al. (1984) converges to within ε in relative accuracy in O(ε^-2h_minN_max) number of iterations, where N_max is the number of paths sharing the maximally shared link, and h_min is the diameter of the network. Based on this complexity result, we also show that the one-source-at-a-time update policy has a complexity bound which is O(n) times smaller than that of the all-at-a-time update policy, where n is the number of nodes in the network. The result of this paper argues for constructing networks with low diameter for the purpose of reducing complexity of the network control algorithms. The result also implies that parallelizing the optimal routing algorithm over the network nodes is beneficial     

Programmable interconnects speed system verification

A family of CMOS integrated circuits called field programmable interconnect components (FPICs) that can provide designers with the high-density interconnect architectures for making programmable hardware a reality is discussed. The FPIC devices address a broad spectrum of interconnect needs, including system prototypes and breadboards, user-specific/configurable printed circuit boards (PCBs), application configurable processors, test interfaces, and programmable connector and switching matrix applications. Using FPIC devices for system prototyping, in conjunction with other programmable components (programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors, microcontrollers, DSP, and programmable memory) enhance the design verification process, allowing faster, more flexible, and thorough product integration. Field programmable circuit boards (FPCBs) designed to take advantage of the high density interconnect and observability of FPIC devices and a FPIC/FPCB development environment are described     

Flexibility of interconnection structures for field-programmablegate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility     

Multistage network with globally controlled switching stages and its implementation using optical multi-interconnection modules

Plane-to-plane guided-wave-based interconnection modules are proposed as building blocks for scalable optoelectronic multistage interconnection networks (MINs). This approach leads naturally to a MIN paradigm based not on cascading switching stages containing several size-reduced crossbars, as in the shuffle-exchange (SE) networks, but on cascading permutation-reduced crossbars instead, one per stage. The interest of such an architecture lies in the control simplicity and scalability potential. Transparent circuit switching for permutation routing is possible in such an unbuffered "globally switched" multistage interconnection network (GSMIN). Preliminary experiments using fiber-based interconnection modules are presented. Performance analysis and simulation of a buffered GSMIN is also studied for packet routing purposes.     

On Multicast Routing for Wavelength-Routed WDM Networks with Dynamic Membership

Future broadband networks must support integrated services and offer flexible bandwidth usage. In our previous work in [1], we explored the optical link control (OLC) layer on the top of optical layer that enables the possibility of bandwidth on-demand (BoD) service directly over wavelength division multiplexed (WDM) networks. Today, more and more applications and services such as video-conferencing software and Virtual LAN service require multicast support over the underlying networks. Currently, it is difficult to provide wavelength multicast over optical switches without optical/electronic conversions although the conversion takes extra cost. In this paper, based on the proposed wavelength router architecture (equipped with ATM switches to offer O/E and E/O conversions when necessary), a dynamic multicast routing algorithm is proposed to furnish multicast services over WDM networks. The goal is to join a new group member into the multicast tree so that the cost, including the link cost and the optical/electronic conversion cost, is kept as low as possible. The same algorithm can be applied to other wavelength routing architectures with redefinition of electronic copy cost. The effectiveness of the proposed wavelength router architecture as well as the dynamic multicast algorithm is evaluated by simulation.     

On blocking probability of multicast networks

Multicast is a vital operation in both broad-band integrated services digital networks (BISDN) and scalable parallel computers. We look into the issue of supporting multicast in the widely used three-stage Clos network or υ(m, n, r) network. Previous work has shown that a nonblocking υ(m, n, r) multicast network requires a much higher network cost than a υ(m, n, r) permutation network. However, little has been known on the blocking behavior of the υ(m, n, r) multicast network with only a comparable network cost to a permutation network. We first develop an analytical model for the blocking probability of the υ(m, n, r) multicast network and then study the blocking behavior of the network under various routing control strategies through simulations. Our analytical and simulation results show that a υ(m, n, r) network with a small number of middle switches m, such as m=n+c or dn, where c and d are small constants, is almost nonblocking for multicast connections, although theoretically it requires m⩾Θ(n(log r/log log r)) to achieve nonblocking for multicast connections. We also demonstrate that routing control strategies are effective for reducing the blocking probability of the multicast network. The best routing control strategy can provide a factor of two to three performance improvement over random routing. The results indicate that a υ(m, n, r) network with a comparable cost to a permutation network can provide cost-effective support for multicast communication     

A novel and efficient routing architecture for multi-FPGA systems

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable interconnect devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed, and previous research has shown that the partial crossbar is one of the best existing architectures. In this paper, we propose a new routing architecture, called the hybrid complete-graph and partial-crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs. We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and interchip routing tools were developed, with particular attention paid to architecture-appropriate interchip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 25% more. Furthermore, the critical path delay for designs implemented on the partial crossbar were on average 20% more than the HCGP architecture and up to 43% more. Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture-the proportion of hard-wired connections versus programmable connections-to determine its best value     

Comments on “On amplitude and frequency demodulation usingenergy operators”

The authors comment that while testing some of the results obtained by Maragos, Kaiser and Quatieri (see ibid., vol.41, no.4, p.1532-50, 1993) with a discrete FM signal of the form x(n)=Acos(φ(n)) where φ(n)=Ω_cn+Ω_m /Ω_fsin(Ω_fn)+&thetas; they noticed that the error in the instantaneous frequency increased as Ω_f increased. One would hope that frequency tracking of a constant frequency sinusoidal signal would be very accurate. However, this does not agree with one of their proposition as there is an error in its proof     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

基于FPGA的开关盒互连容错算法的研究

FPGA主要由两个基本部分组成,一是可配置逻辑部件,另一部分就是互联网络,负责对可配置逻辑块间的通信。FPGA内部大约80%的晶体管都是作为可编程开关和缓冲器来完成可编程路由网络工作的。文中主要对出现错误的开关盒阵列中可执行的路径数量进行评估,并且使用算法找到合适的路径,避开错误。     

Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.     

High-temperature superconductor resonators and phase shifters

High-T_c resonators and hybrid digital phase shifters have been designed, fabricated, and tested. The YBa₂Cu₃O_7-δ (YBCO) films used were off-axis sputtered onto 0.5-mm-thick [100] LaAlO₃ substrates and have surface impedances at 10 GHz as low as 20 μΩ at 4.2 K and 300 μΩ at 77 K. The dielectric constant of the LaAlO₃ substrates was measured using straight-line and ring resonator techniques. The superconductor straight-line resonator, which uses silver as its ground plane, has a moderately high Q factor and has an electromagnetic feedthrough level below -65 dB up to 10 GHz. The authors also report the first demonstration of a semiconductor/superconductor microwave digital phase shifter. YBCO film was used to form the circuit, with semiconductor p-i-n diodes serving as switches. A 4-b superconductor phase-shifter design is also presented along with simulation results that indicate maximum total insertion loss (which occurs with all bits forward-biased) at 77 K to be 1.1 dB at 10 GHz     

Partitioned optical passive star (POPS) multiprocessorinterconnection networks with distributed control

This paper presents a partitioned optical passive star (POPS) interconnection topology and a control methodology that, together, provide the high throughput and low latency required for tightly coupled multiprocessor interconnection applications. The POPS topology has constant and symmetric optical coupler fanout and only one coupler between any two nodes of the network. Distributed control is based on the state sequence routing paradigm which multiplexes the network between a small set of control states and defines control operations to be transformations of those states. These networks have highly scalable characteristics for optical power budget, resource count, and message latency. Optical power is uniformly distributed and the size of the system is not directly limited by the power budget. Resource complexity grows as O(n) for the couplers, O(n√n) for transceivers, and O[√nlog(n)] for control. We present analysis and simulation studies which demonstrate the ability of a POPS network to support large scale parallel processing (1024 nodes) using current device and coupler technology     

Array interconnection for rearrangeable 2-D MEMS optical switch

Two-dimensional (2-D) microelectromechanical systems (MEMS) optical switches can be constructed by arranging the MEMS-actuated micromirrors as an array. We consider here the switching capability, routing, and optimization of the rectangular array interconnection on which the capability and efficiency of 2-D MEMS switches depend. The switching capability of a rectangular array is proved analytically. Two routing algorithms, namely, the most-bend routing and the least-bend routing, are developed, which, respectively, maximize and minimize the number of 2 /spl times/ 2 switches in the "bend" state. A method of counting the number of permutations realizable with a given number of switches in the "bend" state is proposed to evaluate the performance of both routing schemes. The understanding of the underlying interconnection pattern enables us to study the problem of constructing rearrangeable optical switches of arbitrary size.     

A non-Shannon-type conditional inequality of information quantities

Given n discrete random variables Ω={X₁,…,X_n}, associated with any subset α of {1,2,…,n}, there is a joint entropy H(X_α) where X_α={X_i: i∈α}. This can be viewed as a function defined on 2^{1,2,…,n} taking values in [0, +∞). We call this function the entropy function of Ω. The nonnegativity of the joint entropies implies that this function is nonnegative; the nonnegativity of the conditional joint entropies implies that this function is nondecreasing; and the nonnegativity of the conditional mutual information implies that this function is two-alternative. These properties are the so-called basic information inequalities of Shannon's information measures. An entropy function can be viewed as a 2ⁿ -1-dimensional vector where the coordinates are indexed by the subsets of the ground set {1,2,…,n}. As introduced by Yeng (see ibid., vol.43, no.6, p.1923-34, 1997) Γ_n stands for the cone in IR(2ⁿ-1) consisting of all vectors which have all these properties. Let Γ_n* be the set of all 2ⁿ -1-dimensional vectors which correspond to the entropy functions of some sets of n discrete random variables. A fundamental information-theoretic problem is whether or not Γ¯_n*=Γ_n. Here Γ¯_n * stands for the closure of the set Γ_n*. We show that Γ¯_n* is a convex cone, Γ₂*=Γ₂, Γ₃*≠Γ₃, but Γ¯₃ *=Γ₃. For four random variables, we have discovered a conditional inequality which is not implied by the basic information inequalities of the same set of random variables. This lends an evidence to the plausible conjecture that Γ¯_n*≠Γ_n for n>3     

Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA

A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications. Two criteria are proposed and used as figure-of-merit for evaluating different FPGA interconnect architectures. The proposed approach is based on the number of available paths between pairs of end points and the probability to establish a one-to-one mapping between all input and output end points. A probabilistic approach is also presented to evaluate the fault-tolerant routing of the entire FPGA by connecting switch blocks in chains, as required for testing and to account for the input–output (I/O) pin restrictions of an FPGA chip. All possible interconnect faults for programmable switches and wiring channels are considered in the fault model. The proposed method is applicable to arbitrary switch block structures. Experimental results on commercial as well as academic designed FPGAs are presented and analyzed.     

Novel algorithm for Clos-type networks

A new routing algorithm for controlling nonblocking Clos-type permutation networks is presented. Unlike previous algorithms based on matrix decomposition and looping techniques, the algorithm uses a new method called scheduling, does not use iterations, and has execution time 0(Nr/sup 1/2/) where N is the total number of ports, and r is the number of first-stage switches.<>     

Design of wavelength converting switches for optical burst switching

Optical burst switching (OBS) is an experimental network technology that enables the construction of very high-capacity routers, using optical data paths and electronic control. In this paper, we study wavelength converting switches using tunable lasers and wavelength grating routers, that are suitable for use in OBS systems and evaluate their performance. We show how the routing problem for these switches can be formulated as a combinatorial puzzle or game, in which the design of the game board corresponds to the pattern of permutation used at the input sections of the switch. We use this to show how the permutation pattern affects the performance of the switch, and to facilitate the design of permutation patterns that yield the best performance. We give upper bounds on the number of different wavelength channels that can be routed through such switches (regardless of the permutation pattern), and show that for 2/spl times/2 switches, there is a simple permutation pattern that achieves these bounds. For larger switches, randomized permutation patterns produce the best results. We study the performance of optical burst switches using wavelength converting switches based on several different permutation patterns. We also present a novel routing algorithm called the most available wavelength assignment and evaluate its benefits in improving the switch throughput. Our results show that for a typical configuration, the switch with the best permutation pattern has more than 87% of the throughput of a fully nonblocking switch.