用红外光弹测量功率整流管工艺中的残余应力

利用红外光弹系统，采用森纳蒙特（Ｓｅｎａｒｍｏｎｔ）补偿法，对功率整流管制备过程中扩散和镀镍工艺所引入的残余应力进行了测量和讨论．获得扩硼铝、扩磷和镀镍硅片中的应力值，并给出了残余应力在硅衬底片中的分布图．     

硅晶片氧化应力的红外光弹性测量及研究

本文利用红外激光光弹性仪,采用光测弹性力学中的Senarmont补偿法,解决了硅晶片小数级条纹值定量测量问题.在考虑硅晶体光弹性效应各向异性的基础上,实测了(111)、(100)单晶硅片的原始应力及氧化应力.对硅晶片原始应力的产生与消除、氧化应力在硅中的分布、氧化应力与氧化层厚度的关系、氧化应力随时间的变化等进行了研究.     

硅光单体电源铝背场吸杂对非平衡少子寿命的影响

采用φ100mm厚度400μm、电阻率为0.8～2Ω·cm的p(100)CZ硅片制作硅光单体电源,并对RTP和铝背场烧结工艺进行了研究.实验发现:快速热退火工艺对硅片少子寿命产生一定影响.铝背场烧结和适当的快速热处理促成了硅片界面晶格应力对重金属杂质的吸附作用,并减少了载流子的复合中心,从而提高了光生载流子的扩散长度,提高了非平衡少子寿命.     

硅光单体电源铝背场吸杂对非平衡少子寿命的影响

采用φ100mm厚度400μm、电阻率为0.8～2Ω·cm的p(100)CZ硅片制作硅光单体电源,并对RTP和铝背场烧结工艺进行了研究.实验发现:快速热退火工艺对硅片少子寿命产生一定影响.铝背场烧结和适当的快速热处理促成了硅片界面晶格应力对重金属杂质的吸附作用,并减少了载流子的复合中心,从而提高了光生载流子的扩散长度,提高了非平衡少子寿命.     

液氮冲击中InSb焦平面探测器热应力计算

液氮冲击中InSb焦平面探测器的局部分层、局部碎裂制约着其成品率的提高.为分析液氮冲击中发生在InSb焦平面探测器中的潜在失效模式,我们借助C.H.Hsueh提出的适用于弹性多层体系热应力计算理论,结合InSb焦平面探测器的典型结构,忽略铟柱阵列的影响,得到了InSb焦平面探测器中心区域热应变和热应力沿厚度方向的分布.依据热应变和热应力分布,我们认为液氮冲击中InSb芯片和底充胶均处于拉应力状态,硅读出电路上边2/3部分处于压应力状态,下边1/3部分处于拉应力状态.整个探测器四角往上翘曲,中心区域往下凸起.这些计算结果为后续探测器组件封装中平衡复合物结构的设计提供了理论参考.     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

硅晶片应力的红外光弹测量

本文介绍测量硅晶片应力的红外光弹系统及方法。对硅晶片进行了四点简支梁模型的加压实验,其应力测量的结果与理论计算的结果基本符合;并测量了某些半导体器件模拟工艺在硅片内引入的应力。     

单片集成MEMS中的阳极键合工艺

分析了阳极键合工艺的原理及其工艺条件对CMOS电路的影响，并通过理论分析和实验研究了单片集成MEMS中的两种阳极键合方法：对于玻璃在硅片上方的键合方式，通过在电路部分上方玻璃上腐蚀一定深度的腔及用氮化硅层保护电路可以在很大程度上减轻阳极键合工艺的影响；而玻璃在硅片下方的键合方式，硅片上的电路几乎不受阳极键合工艺的影响，两种方法各有优缺点。     

高温工艺中硅片的翘曲

通过硅片高温热处理实验研究了热自理工艺和表面状态对硅片高温弯曲度变化的影响，高温工艺中坚直装片引起的形变较小，研磨硅片经过适当化学腐蚀可明显降低高温翘曲。     

用于监测硅片应力的红外光弹仪

为检测硅片在制造工艺中的应力变化,研制了可用于硅片应力检测/监测的红外光弹(IRPE)系统,获得了芯片的红外光弹图像.利用该系统得出了硅通孔(TSV)结构在退火过程中的应力变化,并发现虽然制造技术和工艺完全一样,但每个TSV的初始残余应力是不同的.不同的TSV取得零应力的温度点也不相同,然而当温度达到一定值时,所有TSV都将保持零应力状态.此外,该系统也用于晶圆键合质量的评价,相对于一般红外显微镜,其检测效果更佳,与超声法相比,其检测效果相当,但效率更高且不需耦合剂.     

Photoelastic stress evaluation and defect monitoring in 300-mm-wafer manufacturing

Process monitoring and tool characterization on product wafers require rapid non-contact and non-destructive evaluation methods. Because all process steps are more or less related to stress in the crystal, the photoelastic stress evaluation by infrared polarimetry is a suitable method for process screening both in wafer and IC manufacturing. It is shown that the full wafer imaging by scanning infrared depolarization can be applied to different steps of wafer manufacturing. After a short introduction into the method and technical realization of on-line photoelastic measurements, the concept of defect-related stress monitoring and process screening is demonstrated for slicing, grinding, lapping, etching, polishing and thermal treatment.     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

A technique for characterizing surface recombination in silicon wafers based on thermal-emission measurements

A noncontact technique for the measurement of the surface-recombination rate in silicon wafers is suggested. A wafer under study is excited optically in the spectral region of intrinsic absorption, and the excitation-wavelength dependence of the power of the wafer thermal emission beyond the intrinsic-absorption edge is examined. The surface-recombination rate is determined from the ratio of intensities of the wafer thermal emission in the wavelength range 3–5 μm recorded under excitation with two laser diodes with wavelengths of 863 and 966 nm. Wafers subjected to different surface treatments were tested; at 230°C, rates on the order of 10⁴ cm/s were measured after mechanical polishing and 10³ cm/s after etching in CP-4A etchant. The applicability of the method is discussed, and the measurement error as a function of the wafer and light-source parameters is considered.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Stress distribution on [100] Si wafer mapped by novel I-V analysis of MOS tunneling diodes

The current-voltage (I-V) characteristics of metal-oxide-semiconductor tunneling diodes distributed over a 3-in Si wafer were analyzed to investigate the stress distribution on the wafer. Generally, the substrate injection saturation current (J/sub sat/) decreases as the gate injection leakage current (J/sub g/) increases, the latter being dominated by oxide thickness via a trap related mechanism. A universal curve to fit all analyzed data was found and it is suggested that devices with extremely high (low) J/sub sat/ at a given J/sub g/ should be located in areas of the silicon lattice with relatively high external compressive (tensile) stress because of the stress-induced bandgap variation effect. The mapped locations of the highly stressed devices on a 3-in [100] Si wafer correspond to the patterns of slips caused by thermal stress during rapid thermal processing, as described in previous reports.     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

硅单晶片中的氧及对后续缺陷的影响

通过测量硅晶棒不同部位的氧含量,分析了氧在硅晶棒中的分布规律。结合高温氧化后的缺陷观察结果,研究了氧含量及后续高温生产工艺对硅晶体中缺陷数量的影响。对不同氧含量的两种硅单晶片所生产的功率集成电路进行了失效分析。结果表明,硅单晶片中的氧含量对产品成品率具有重要影响。当氧含量在1.77×10¹⁸~1.87×10¹⁸atoms/cm³及以上时,硅单晶片边缘出现明显的位错排,断面存在大量层错和位错缺陷,部分缺陷进入外延层中的晶体管,造成该处晶体管结漏电。相反,当氧含量偏低时,硅单晶片内的缺陷较少且分布不均,使得硅单晶片受到金属污染时不能有效吸杂而产生失效。