一种快速全数字锁相环

本文根据突发式数字通信快速锁相要求,提出一种位同步信号提取的新的快速全数字锁相环方案.它比一般数字锁相环捕捉速度最大可以提高N/2倍,且环路的同步时间与量化相位误差的矛盾也得到了解决,因而环路精度也大有改善.本文主要以一阶环为例讨论位同步信号提取.     

Fully digital strategy for fast calibration and test of ΣΔ ADCs

This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADCs. Simulation results showed a detection sensitivity on specifications parameters of up to −100 dB. The proposed method can also help to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.     

Optimum digital phase-locked loops

The optimum discrete filters to track phase and frequency steps in the presence of additive white Gaussian noise are derived, and are found to be equivalent to the baseband models of 1st- and 2nd-order digital phase-locked loops, respectively. Practical design parameters are presented.     

A digital phase-locked loop for generating frequency discriminating digital words

The circuit configuration of the DPLL described in this paper is a modified version of the DPLL recently reported by the authors. Fast and symmetrical tracking has been achieved by the modified DPLL retaining the original properties of wide locking range and low frequency capability as an FM discriminator and frequency multiplier. Also, it is operable in a number of modes defined by their phases (0°, 180°, and 90°) and the frequency discriminating code X is scalable by the phase-lock logic design.     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A survey of digital phase-locked loops

The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers. This survey is particularly motivated by the fact that microprocessor technology is advancing rapidly to the extent that sophisticated and flexible signal processing algorithms for communications and control can be realized in the digital domain. In fact, it is anticipated that the use of this signal processing technology will continue to expand rapidly in the development of advanced communications and tracking receivers, e.g., all digital modems. Consequently, one major purpose of this paper is to provide the reader with a survey and an overview of the theoretical and experimental work accomplished to date, thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature. In addition, the authors feel that a tutorial article revealing the various theories, their relationships to one another, their shortcomings, their advantages and the assumptions on which each is based, would be of tremendous value to the engineer trying to decide what particular analysis procedure is applicable to his peculiar problem. Consequently, a byproduct of this presentation will be to point out unsolved problems of practical interest. A broad class of digital modulation techniques, viz. I-Q modulations and demodulation, are studied in a rather general way.     

Novel quick-response, digital phase-locked loop

The structure of a conventional digital phase-locked loop has been modified to improve its transient response. The superiority of the new loop has been established analytically and by computer simulation results     

Fully digital strategy for fast calibration and test of ΣΔ ADC's

This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADC's. Simulation results showed a detection sensitivity on specifications parameters of up to −100 dB. The proposed method can also help to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.     

A high lock-in speed digital phase-locked loop

A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported     

Jitter reduction of a digital phase-locked loop

This letter presents a jitter reduction technique for the digital phase-locked loop proposed by G. Pasternack and R. L. Whalin. In this technique, the lower N bits of load data from the first register are cut down and loaded into the final register as the round-off data. According to the experimental results, rounding off 5 bits in the second-order loop causes jitter to be reduced by 19.5 dB; therefore, this technique is useful for carrier tracking applications.     

Analogue?digital phase-locked loop for alternating current quartz electrogravimetry

Requirements for frequency-voltage conversion in alternating current (AC) electrogravimetry are introduced. A new frequency-voltage conversion system based on a double tuning analogue-digital phase-locked loop is proposed. The reported results prove its reliability for AC electrogravimetry measurements     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

数字锁相环综评

本文旨在对数字锁相环(DPLL'S)三十年来在理论和实验方面的发展,作一系统的综述和评论.文中系统地阐述了各种理论,指出了它们之间的关系,以及它们是在什么假设前题下建立的.各种理论有什么优缺点,顺便也指出了尚待解决的问题.这篇评论充分注意到由于微处理技术迅速的发展,对通讯和控制信号的各种算法已能在数字领域内方便地实现.因此,本文把重点放在介绍自适应数字锁相环上.最后,文中展望了DPLL的研究和发展的前景.     

A digitally controlled phase-locked loop with a digitalphase-frequency detector for fast acquisition

A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-μm CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively     

Comparison between first-order digital and analogue phase-locked loops

The letter deals with a comparison between a binary quantised digital phase-locked loop and a conventional one. It is shown that, under the condition of equal acquisition times, a digital loop performs better for low signal/noise ratios.     

Chaos and bifurcation in a third-order digital phase-locked loop

Nonlinear dynamics of a third-order zero crossing digital phase locked loop (ZCDPLL) has been investigated. It has been observed that, while first and second-order ZCDPLLs show period doubling route to chaos, a third-order ZCDPLL manifests a disjoint periodic attractor in its route to chaos. Also, the complexity and predictability of the system dynamics have been characterized by using nonlinear dynamical measures such as Lyapunov exponent, Kaplan–York dimension, correlation dimension and Kolmogorov entropy. All the results show that the chaos in a third-order ZCDPLL is low dimensional.     

A digital phase-locked loop for generating frequency discriminating codes and frequency multiplication

A new digital phase-locked loop system realizale by a few off-the shelf digital ICs is described. The system is locked by tracking the input square wave and produces an output binary code whose value is proportional to the input frequency. It is characterized by wide locking range and fast capture time down to very low frequencies (<1 Hz) and suited to low frequency multiplication. Asymmetry in capture time, however, limits its use as an FM demodulator to only slowly varying signals.     

A precise digital phase shifter using a phase-locked loop

A phase-locked loop containing a voltage-controlled oscillator (v.c.o.) synchronised to a harmonic of its fundamental output frequency may be used to form an attractive digital phase shifter providing low phase error with relatively simple circuitry and control requirements. Phase increments of 2?/n radians are obtained, where n is the order of harmonic used.