A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

A 0.18μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.     

DC offset control with application in a zero-IF 0.18 μm CMOS Bluetooth receiver chain

A compact DC offset correction circuit based on the intrinsic properties of quasi-floating gate (QFG) transistors is presented. The proposed scheme uses a tuning mechanism to make its initial response faster improving the traditional large settling time of these circuits. A zero-IF baseband receiver chain suitable for Bluetooth that includes the proposed dc offset correction has been designed in a 0.18 μm CMOS technology at 1.2 V supply voltage.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.     

A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology

A fast-settling all-digital phase-locked loop (ADPLL) is presented in this paper. We propose two techniques for reducing the settling time of an ADPLL, i.e. the oscillator tuning word (OTW) presetting technique and counter-based mode switching controller (CB-MSC). In the first technique, the OTW is preset in process, voltage, and temperature (PVT) calibration mode (P-mode), which leads to the digitally controlled oscillator being initialized with a frequency closer to the target. In the second technique, the CB-MSC is used to shorten the mode switching time. A prototype 1.9 GHz ADPLL with a 13 MHz reference is implemented in 0.18 μm CMOS process. Measurements show that the proposed techniques reduce the settling time by about 33 %. The proposed ADPLL settles within 130 reference cycles and presents a phase noise of ?116 dBc/Hz@1 MHz.     

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm².     

High LO-RF isolation of zero-IF mixer in 0.18 μm CMOS technology

In this study, we introduce a zero-IF sub-harmonic mixer with high isolation in the 5 GHz band using 0.18 μm CMOS technology. Placing an LC-Tank between the class AB stage and the mixer core improves the isolation between the LO to RF at low supply voltage. The measured isolation is 48 dB between the LO and RF ports, and the 9.5 dB conversion gain is achieved with a supply voltage of 7 mA at 2.5 V. In order to alleviate the degradation of linearity due to the high conversion gain, we adopt the class AB stage as RF input stage. The measured IIP₃ is −7.5 dBm. This work was supported by National Science Council of Taiwan, ROC under contract no. NSC94-2220-E-005-002.     

A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differential voltage buffer with additional gain boost, high linear voltage-to-voltage conversion and low output impedance is introduced. In this work, a fourth-order filter is implemented. Simulation results show the 750 MHz cutoff frequency with less than ?50 dB IM3 for a 300 mVpp input. The power consumption for this filter is 6 mW at a 1.2-V supply.     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

0.18μm SOI工艺技术

最近 ,三菱电机公司开发出了一种具有高可靠性的 0 18μｍＳＯＩ工艺技术。通过这种技术 ,由ＣＭＯＳ器件实现 2 5Ｇｂ/ｓ的超高速通信用ＩＣ。而且 ,业已证实采用大容量ＳＲＡＭＴＥＧ (ＴｅｓｔＥｌｅｍｅｎｔＧｒｏｕｐ :特性评价器件 )有可能实现大规模高速ＬＳＩ。1　局部沟槽隔离技术(ａ) 0 18μｍＳＯＩ技术的开发情况所谓的ＳＯＩ技术 ,就是在Ｓｉ基板的绝缘膜 (埋入氧化膜 )上形成单晶硅层 (ＳＯＩ层 )结构。与普通的Ｓｉ基板器件在基板上直接形成晶体管的情况相反 ,ＳＯＩ器件则是在薄的ＳＯＩ层上形成晶体管 ,由于可以缩小源 …     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².