Optical true time delay unit with wide range and high resolution for phased array beamforming

Photonic Network Communications - An optical true time delay (OTTD) unit based on uniform fiber Bragg gratings, photonic crystal fiber and wavelength converter array is proposed for the phased...     

A new time delay estimator based on ETDE

In this paper, we address the problem of online subsample time delay estimation of narrowband signals of known center frequency. We propose a new so-called mixed modulated Lagrange explicit time delay estimation (MMLETDE) algorithm and study its performance through computer simulations. The MMLETDE is a modulated Lagrange ETDE, but the delay estimate adaptation process is based on the truncated sinc fractional delay filter algorithm. We provide theoretical derivations for our proposed estimator, a proof of its convergence performance, learning characteristics of its error performance surface, and an expression for its delay variance. Using simulations, we show that MMLETDE requires only a small filter order and has no noticeable estimation bias over a wide frequency range.     

基于分数时延滤波器的宽带数字信号时延的实现

阐述了基于分数时延滤波器的时延方法设计原理,对其中4种代表性的设计方法的时延性能进行了评估,给出宽带数字线性调频信号的时延仿真结果,该方法可用于宽带雷达数字信号处理。     

基于分层结构的空时分组码

提出了一种新的空时编码方法,该方法结合了分层空时BLAST (Bell Layered Space Time)结构及空时分组码STBC (Space Time Block Code)的优点.采用在发射端对发射天线分组,对于每组进行独立的空时分组编码,而在接收端进行分组干扰抑制,并且用奇异值分解方法实现解码.该方法具有高于STBC的频谱利用率和码速率.仿真结果验证了该方法的抗衰落性能优于BLAST.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

基于分数低阶矩的LETDE时延估计算法

依据α稳定分布噪声模型,提出了一种新的时延估计方法——基于分数低阶矩的ETDE(explicit time delay estimation)方法,简称为LETDE(low-order explicit time delay estimation)。该方法以估计误差的p阶矩作为优化准则,有效地抑制了非高斯噪声对估计值的影响。理论分析和计算机仿真实验都表明其具有良好的韧性,同时适用于高斯噪声和α稳定分布脉冲噪声下的时延估计。     

基于短时分数阶傅里叶变换的谱分割算法

多分量非线性调频信号在现代通信和雷达系统中应用越来越广泛,而对其进行有效分析识别的常用算法就是短时分数阶傅里叶变换（Short Time Fractional Fourier Transform,STFRFT）.文章首先讨论了STFRFT的圆特性,证明了它基于高斯旋转窗的非圆性并给出了修正的圆的STFRFT定义;在此基础上研究了时频变换后不同时频点的谱峭度,进而推导出了区域集的谱峭度,并将该区域谱峭度作为谱图上某区域内是否含有信号点的检测因子;最后基于区域集谱峭度的区域增长算法被用于从谱图中盲分割识别出各个非线性调频分量信号.仿真实验验证了所提算法的有效性和鲁棒性.     

一种基于分数延时滤波器的自适应对消技术的研究

针对转发式干扰机发射的干扰信号通过空间耦合对接收机造成的影响,提出了基于LMS算法的自适应对消结构,并针对宽带信号,对结构作出了调整。重点是利用可变分数延时滤波器来实现参考信号与干扰信号时间的对齐,从而达到宽带对消的效果。提出了能够实现可变分数延时滤波器的结构。通过仿真表明该对消结构能够很好地对消宽带干扰。     

A new algorithm for explicit adaptation of time delay

By using an adaptive technique similar to the one developed by Etter and Stearns (1981), a novel constrained algorithm for explicit time delay estimation (TDE) is derived. The adaptive process provides an unbiased delay estimate and its respective performance surface, learning characteristics and delay variance will be given. The mean-square error surface, though a function of the estimated delay only, is multimodal and proper initialization is required to guarantee global convergence. Simulation results are included to validate the convergence behavior of the TDE system     

A new architecture for the Viterbi decoder for code rate k/n

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time     

一种大量程双弹簧式光纤光栅位错计

设计了一种大量程双弹簧式光纤光栅位错计。选 用弹簧作为位移-力转化元件,使光纤布拉格光栅 (fiber Bragg grating,简称FBG)所在基体发生轴向应变进而得到中心波长变化量。理论分 析了FBG位错 计机械结构与基体之间的位移传递关系,给出了位错计的理论灵敏度系数公式。以位移量为 变化参数,对 FBG位错计进行了标定试验并根据数据进行传感器静态特性分析。结果表明,位错计的双向 线性度分别为 2.445%和2.386%;迟滞性分别为 3.385%和1.237%;灵敏度系数分别为34.93pm/cm和31.20pm/cm。该 FBG位错计结构简单、量程大、精度高、抗电磁干扰且可以实现温度自补偿。可应用于恶劣 以及复杂的地下工程结构长期的相对沉降远程监测。     

A hierarchical architecture based on traveling salesman problem for hybrid wireless network-on-chip

Wireless Networks - The increased latency and power consumption are the major challenges of traditional wired Network-on-Chip (NoC). The Wireless NoC (WNoC) architecture is regarded as a novel...     

超宽带雷达中基于小波变换的时延估计方法

在分析时延估计方法及存在的问题的基础上，为提高时延估计的准确性和算法速度，通过小波的分解与重构算法在不同的分辨率级别上进行时延估计，得出了超宽带线性调频雷达中基于小波多分辨方法的时延估计新算法。由于这种算法对于信号及噪声的特性并未提出要求，因而适合于超宽带雷达中的时延估计。     

基于FPGA的大动态范围数字AGC的实现

数字中频接收机中,采用可变增益放大器AD603、数字可控增益放大器AD8320和FPGA实现大动态范围的教字自动增益控制(AGC).该设计充分利用AD9220的两个指示输入信号范围的输出端口和FPGA编程同时控制可变增益放大器和数字可控增益放大器,即使用同一控制字同时控制两个增益,从而实现增大AGC动态范围,简化电子设备调试,提高接收机工作性能的目的.     

基于FPGA的大动态范围数字AGC的实现

数字中频接收机中,采用可变增益放大器AD603、数字可控增益放大器AD8320和FPGA实现大动态范围的数字自动增益控制（AGC）。该设计充分利用AD9220的两个指示输入信号范围的输出端口和FPGA编程同时控制可变增益放大器和数字可控增益放大器,即使用同一控制字同时控制两个增益,从而实现增大AGC动态范围,简化电子设备调试,提高接收机工作性能的目的。     

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

An LO architecture with novel wide locking range,quadrature output RILFDs and ILROs for cognitive radio applications

In this paper, a wide locking range, quadrature output ring type injection locked frequency divider (ILFD) is presented for division ratios of 3 and 4. This ILFD proposes a novel injection scheme that shapes the injection signal to a proper form and provides a convenient situation for divider locking. Furthermore, two new wide locking range, low power consumption, injection locked ring oscillators (ILROs) are proposed for quadrature generation in local oscillator architectures. A novel cognitive radio quadrature local oscillator (LO) architecture is presented by utilizing the proposed ILFDs and ILROs to verify the effectiveness of the proposed circuits. Moreover, a new technique is implemented on the LO architecture to widen the frequency range without consuming any extra power. Because of using a single LC tank, this architecture is very compact. Also, it has the benefit of low power consumption and low output phase noise.     

A new Reed-Solomon code decoding algorithm based on Newton'sinterpolation

A Reed-Solomon code decoding algorithm based on Newton's interpolation is presented. This algorithm has as main application fast generalized-minimum-distance decoding of Reed-Solomon codes. It uses a modified Berlekamp-Massey algorithm to perform all necessary generalized-minimum-distance decoding steps in only one run. With a time-domain form of the new decoder the overall asymptotic generalized-minimum-distance decoding complexity becomes O(dn), with n the length and d the distance of the code (including the calculation of all error locations and values). This asymptotic complexity is optimal. Other applications are the possibility of fast decoding of Reed-Solomon codes with adaptive redundancy and a general parallel decoding algorithm with zero delay     

A new time delay estimation in subbands for resolving multiplespecular reflections

A new time delay estimation procedure is proposed using the multiresolution analysis framework through a discrete wavelet transform (DWT). Once the signals are decomposed, the time delays are estimated iteratively in each subband using two different adaptation mechanisms that minimize the mean squared error (MSE) between the reference and primary signals in the corresponding subband and level. The localization of the minima of the MSE curves at different levels and subbands is used in order to arrive at the time delay estimates. The proposed scheme is then applied to a real-life problem of underwater target detection from acoustic backscattered data     

A PAPR reduction scheme based on a new spreading code in optical direct detection OFDM system

In this paper, we propose and experimentally demonstrate a peak-to-average power ratio (PAPR) reduction scheme based on a new spreading code in direct detection optical orthogonal frequency division multiplexing (OFDM) system. The new spreading code with low cross correlation and high auto-correlation can support \(2N+1\) users. Thus, \(2N+1\) users or data symbols can be transmitted over only N subcarriers. The experimental results show that, after transmission over 70 km single-mode fiber, at the bit error rate of \(10^{-3}\), with fiber launch power of 2.75 dBm, the receiver sensitivity can be improved 2.1 dB by using the proposed scheme based on new spreading code. The PAPR can be reduced about 4.6 dB, compared with the original OFDM signal at a complementary cumulative distribution function of \(10^{-4}\).