Hierarchical simulation of transport in silicon nanowire transistors

We propose a very fast hierarchical simulator to study the transport properties of silicon nanowire FETs. We obtain the transverse wave functions and the longitudinal effective masses and band-edges of the lowest conduction bands from a nearest-neighbor sp ³ d ⁵ s ^* tight-binding study of an infinite nanowire with null external potential. Then we plug these parameters into a self-consistent Poisson-Schrödinger solver, using an effective mass approach and considering the bands decoupled. We apply this method, which gives quantitatively correct results with notable time savings, for the simulation of transport in two different silicon nanowire FETs.     

Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor

In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.     

Microscopic noise simulation of long- and short-channel nMOSFETs by a deterministic approach

We compute small-signal and noise quantities of nMOSFETs with different channel lengths with a fully self-consistent and deterministic Poisson, Schrödinger, and Boltzmann equation solver. We show how noise qualitatively changes due to short-channel effects and how noise is generated in the domain of ballistic transport. Furthermore, we inspect the suppression of noise due to the Pauli principle and due to the coupling to the fluctuations of the potential.     

Phonon exacerbated quantum interference effects in III-V nanowire transistors

In recent years, a great deal of attention has been focused on the development of quantum wire transistors as a means of extending Moore’s Law. Here we present, results of fully three-dimensional, self-consistent quantum mechanical device simulations of InAs tri-gate nanowire transistor (NWT). The effects of inelastic scattering have been included as real-space self-energy terms. We find that the position of dopant atoms in these devices can lead a reduction in the amount of scattering the carriers experience. We find that the combination of deeply buried dopant atoms and the high energy localization of polar optical phonon processes allow devices to recover their ballistic behavior even in the presence of strong inelastic phonon processes. However, we find that dopant atoms close to the source-channel interface cause severe quantum interference effects leading to significant performance reduction.     

Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.     

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.     

Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Journal of Computational Electronics - This work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical...     

射频宽带低噪声放大器设计

介绍了射频宽带放大器的设计原理及流程。设计实现的射频宽带低噪声放大器,采用分立器件和微带线匹配,选用Agilent公司生产的低噪声增强赝配高电子迁移率晶体管ATF-551M4,用ADS软件进行设计、仿真和优化,实现了在1.1GHz～2.2GHz范围内,增益24dB以上,噪声系数小于1.2dB的两级宽带低噪声放大器设计。由于设计频带覆盖了多个通信常用频点,因此决定此低噪声放大器的应用会十分广泛。最后利用ProtelDXP软件对电路进行了版图设计,并在FR4基板上实现了该设计,给出了实测结果。     

Simulation study of temperature sensitivity of silicon nanowire transistors with different types of orientations

This paper presents the temperature characteristics of a silicon nanowire transistor and its use as a temperature sensor. The OMEN nanowire simulation tool was used to investigate the temperature characteristics of the transistor. Current–voltage characteristics with different values of temperature for three orientations were simulated. The metal–oxide–semiconductor (MOS) diode connection suggests the use of the silicon nanowire transistor as a temperature nanosensor. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Asymmetric junctionless nanowire TFET with built-in $${n}^{+}$$ source pocket emphasizing on energy band modification

We present a detailed study on a technique to realize a narrow and highly doped built-in \({n}^{+}\) source pocket in an asymmetric junctionless nanowire tunnel field-effect transistor (AJN-TFET). In the proposed structure, a built-in \({n}^{+}\) source pocket is created between the \({p}^{+}\) source and the channel without the need for any separate implantation or epitaxial growth. This leads to band diagram modification by providing a local minimum in the conduction band which results in tunneling width reduction at the source–channel interface in on-state. This leads to an abrupt transition between on- and off-state, improved subthreshold swing (SS) (38 mV/dec), and significant on-current enhancement (\(\sim 2000\) times) at low operating voltage compared with the conventional TFET. We further study the effect of the length of the built-in \({n}^{+}\) source pocket on the AJN-TFET characteristics. The proposed structure overcomes the difficulty in creating a narrow \({n}^{+}\) pocket and thus renders the AJN-TFET device more amenable for the future scaling trend needed in low-power applications.     

Nonlinearity and scaling trends of quasiballistic graphene field-effect transistors targeting RF applications

Journal of Computational Electronics - Graphene field-effect transistors (GFETs) based on ballistic transport represent an emerging nanoelectronics device technology with promise to add a new...     

Hot-carrier induced degradations on RF power characteristics of SiGe heterojunction bipolar transistors

Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs are investigated in this paper. By using the two-tone load-pull measurement, we find that not only the cutoff frequency, but also the output power performances of Si/SiGe HBTs are suffered by the HC stress. In this work, S-parameters and intrinsic elements of an equivalent hybrid-/spl pi/ model were used to validate the HC effects on high-frequency characteristics. With different bias conditions, the degradations of cutoff frequency, power gain, and linearity are found to be worse under constant base-current measurement than that under constant collector-current measurement. The HC-induced degradations on the current gain, transconductance, and ideality-factor of base and collector currents are analyzed to explain the experimental observations.     

锁相环相位噪声的研究与仿真

锁相环在数字电路中一个重要的应用就是作为频率合成器产生高性能的时钟。本文介绍了锁相环的工作原理,重点研究了锁相环输出时钟的相位噪声的影响因素。通过对其线性环路模型进行频域分析,运用反馈控制理论,讨论了环路内各器件的噪声对其输出信号相位噪声的影响。得到了锁相环能良好改善环路带内噪声的分析结果,并且利用ADS搭建仿真电路,验证分析结果,为今后高性能频率合成器的设计和应用提供参考依据。