A novel process variation immune dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z$$^{}$$FET) based on transition metals

Transition metal (TM) electrodes based dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z\(^{2}\)FET) is reported in this paper. The work-function engineering of TM electrodes is used for charge plasma based electrostatic pseudo doping. Work-function difference between TM electrodes and the undoped silicon film induces p\(^{+}\) and n\(^{+}\) regions in the film. TMs exhibit easy tunability of work-function and their CMOS fabrication compatibility pledges for their potential applications as these electrodes. A technology computer-aided design simulation study is performed to provide physical insight into its working mechanism and performance. It exhibits all the inherent characteristics of conventional Z\(^{2}\)FET, viz. zero slope switching, high \(I_{ON}/I_{OFF}\) ratio, lower operating voltages, immunity towards hot electron degradation and gate controlled hysteresis. The detrimental doping control issues, mobility degradation due to heavy doping and statistical random dopant fluctuations can no more obviate the device performance, it results in more process variations immune design. Hence it can be a potential fast switching transistor.     

A novel high-performance H-gate U-channel junctionless FET

A novel high-performance H-shape-gate U-shape-channel junctionless FET (HGUC JL FET) is proposed. Compared with the saddle junctionless FET, the proposed HGUC JL FET shows better subthreshold characteristics and higher on-current. Its electrical properties were extensively investigated by studying the influence of variation of design parameters such as the H-gate thickness, the source/drain extension region height, and the gate oxide thickness and material. Compared with conventional structures, the proposed HGUC JL FET shows better performance, especially on scaling down to several nanometers. The reverse leakage current is also effectively restrained and the \({I}_{\mathrm{on}}\)/\({I}_{\mathrm{off}}\) ratio greatly improved through design optimization.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

A systematic investigation of the integrated effects of gate underlapping,dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of \(\mathrm{SiO}_{2}\) as the gate dielectric. Therefore, a hetero gate dielectric \(\mathrm{SiO}_{2}\) on the drain side and \(\mathrm{HfO}_{2}\) on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.     

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage (\(V_\mathrm{TG}\)) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson’s equation in the lightly doped Si film and employing the physical definition of \(V_\mathrm{TG}\). A numerical simulation study of the transfer characteristics and \(V_\mathrm{TG}\) of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of \(V_\mathrm{TG}\) is performed based on the transconductance change method as already used for conventional metal–oxide–semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on \(V_\mathrm{TG}\) are reported. The dependence of \(V_\mathrm{TG}\) on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Asymmetric junctionless nanowire TFET with built-in $${n}^{+}$$ source pocket emphasizing on energy band modification

We present a detailed study on a technique to realize a narrow and highly doped built-in \({n}^{+}\) source pocket in an asymmetric junctionless nanowire tunnel field-effect transistor (AJN-TFET). In the proposed structure, a built-in \({n}^{+}\) source pocket is created between the \({p}^{+}\) source and the channel without the need for any separate implantation or epitaxial growth. This leads to band diagram modification by providing a local minimum in the conduction band which results in tunneling width reduction at the source–channel interface in on-state. This leads to an abrupt transition between on- and off-state, improved subthreshold swing (SS) (38 mV/dec), and significant on-current enhancement (\(\sim 2000\) times) at low operating voltage compared with the conventional TFET. We further study the effect of the length of the built-in \({n}^{+}\) source pocket on the AJN-TFET characteristics. The proposed structure overcomes the difficulty in creating a narrow \({n}^{+}\) pocket and thus renders the AJN-TFET device more amenable for the future scaling trend needed in low-power applications.     

Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance

In this paper, we aim to explore the potential benefits of using source side only dual-k spacer (Dual-kS) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low power operation at 20 nm gate length. It has been observed from the results that Dual-kS (inner spacer high-k) FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source side and results into improvement in transconductance \((g_{m})\) and output conductance \((g_{ds})\). It was also found that drain side only dual-k spacer (Dual-kD) improves the coupling of the gate fringe field to the underlap region towards the drain side which helps to shift away the drain field from gate edge and results into improvement in output conductance \((g_{ds})\) only at the cost of increase in Miller capacitance. A comparative simulation study has been performed on four different device structures namely both side low-k spacers (conventional), both side dual-k spacer (Dual-kB), Dual-kD and Dual-kS structures. From the simulation study, it was found that that Dual-kS structure has potential to improve \(g_{m}\) by \(\sim \)8.7 %, \(g_{ds}\) by \(\sim \)32.24 %, intrinsic gain \((A_{V0})\) by \(\sim \)11.44 %, early voltage \((V_{EA})\) by \(\sim \)47.59 %, maximum oscillation frequency (\(f_{MAX}\)) by \(\sim \)1.7 % and the ratio of gate-source capacitance and gate-drain capacitance \((C_{gs}/C_{gd})\) by \(\sim \)15.27 % with a slight reduction in the value of unity gain cut-off frequency (\(f_{T}\)) by \(\sim \)0.58 % in comparison to the conventional structure at drain current \((I_{ds})\) of \(10\,\upmu \)A/\(\upmu \)m. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on Dual-kS FinFET structure.     

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, \(\mathrm{I_{ON} , I_{OFF}, V_{T}}\), and the unity gain cut-off frequency \(\mathrm{(f_{T}}\)) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.     

Improved device performance in a CNTFET using La$$_{}$$O$$_{3}$$3 high-$$\kappa $$κ dielectrics

The scaling of MOSFETs is an important and effective way for achieving high performance and low power consumption. One of the bottlenecks for scaling is the physical gate oxide thickness. This paper presents and evaluates a new method for scaling carbon nanotube field-effect transistors (CNTFETs) using \(\hbox {La}_{2}\hbox {O}_{3}\) as a new gate dielectric, which has excellent electrical properties. The proposed CNTFET is simulated using HSPICE. Some of the main digital and analog parameters such as current ratio, subthreshold swing (SS), transconductance, and intrinsic gain have been studied. The simulation results show that the proposed CNTFET outperforms present CNTFETs in terms of current ratio, transconductance, and intrinsic gain.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

Double aperture double-gate vertical high-electron-mobility transistor

In this paper, we propose a double aperture double-gate AlGaN/GaN vertical high-electron-mobility transistor (HEMT) to improve the device characteristics, such as the current and the ON resistance (\(\hbox {\textit{R}}_{\mathrm{ON}}\)). The proposed vertical HEMT results are compared to the conventional single aperture single-gate vertical HEMT of equal dimensions, and increased drain current and lower \(\hbox {\textit{R}}_{\mathrm{ON}}\) are shown. A comprehensive simulation study has also been carried out for the proposed device, to analyse the impact of thickness and doping concentration of aperture, drift region, and current blocking layer. In addition, the effect of different materials in current blocking layer on device characteristics is also studied. The obtained results and their effect on device characteristics have been thoroughly analysed and explained accordingly.     

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

An ultra-low specific on-resistance \((R_\mathrm{{on,sp}})\) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low \(R_\mathrm{{on,sp}}\) is therefore obtained in the FVFP device due to higher drift region doping concentration \((N_\mathrm{{d}})\). A breakdown voltage (BV) of 188V and a \(R_\mathrm{{on,sp}}\) of \(0.9 \hbox { m}\Omega \, \hbox { cm}^{2}\) are realized on a 4.8-\({\upmu }\hbox {m}\)-long drift region, a 7.5-\({\upmu }\hbox {m}\)-thick top-silicon layer and a 0.5-\({\upmu }\hbox {m}\)-thick buried oxide (BOX) layer by our simulation. Eventually, the \(R_\mathrm{{on,sp}}\) for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.     

A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

In this paper, a novel symmetrical structure (SS) of 4H–SiC metal semiconductor field effect transistor (MESFET) as an effective way to improve the breakdown voltage is presented. The key idea in this work is to improve the breakdown voltage, maximum output power density, and frequency parameters of the device using a symmetrical structure with recessed gate. The SS-MESFET modifies the electric field in the drift layer significantly. The influence of the SS-MESFET on the saturation current, breakdown voltage \((\hbox {V}_{\mathrm{BR}})\), and small-signal characteristics of the SS-MESFET are studied by numerical device simulation. Using two-dimensional device simulation, we demonstrate that the breakdown voltage \((\hbox {V}_{\mathrm{BR}})\) improved by factors 2.5 and 3.3 in comparison with an asymmetrical conventional MESFET structure (AC-MESFET) and a symmetrical conventional MESFET structure (SC-MESFET), respectively. Also, the maximum output power density \((\hbox {P}_{\mathrm{max}})\) improved about by 93 and 250 % in comparison with the AC-MESFET and SC-MESFET structures, respectively. So, the SS-MESFET shows the superior maximum available gain (MAG), unilateral power gain (U), and current gain \((\hbox {h}_{12})\) which is presenting the proposed structure is more suitable device for high power microwave applications.     

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by \({\sim }\)900 %), subthreshold swing characteristics (by \({\sim }\)12 %) and Drain Induced Barrier Lowering (DIBL) (by \({\sim }\)56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.     

Quantum analysis based extraction of frequency dependent intrinsic and extrinsic parameters for GEWE-SiNW MOSFET

This paper examines the bias-independent and bias-dependent extrinsic and intrinsic parameters of the gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) metal–oxide–semiconductor field-effect transistor (MOSFET) by considering quantum effects. The results reveal that the effect of extrinsic parameters such as the resistance, capacitance, and inductance of the electrodes is less pronounced in the GEWE-SiNW compared with the conventional SiNW or conventional MOSFET. The intrinsic transconductance of the GEWE-SiNW device can be further improved by tuning the gate metal workfunction difference, which results in shorter time constant and lower parasitic capacitance, making it suitable for radiofrequency integrated circuit (RFIC) design. It is also observed that, in the saturation region, the device exhibits improved transconductance and noticeable reduction in \(C_{\mathrm{sdx}}\) [due to drain-induced barrier lowering (DIBL)] but the parasitic capacitance and time constant also reduce. In addition, a non-quasi-static small-signal model has been studied in terms of Z and Y parameters; the results show good agreement with the results of three-dimensional (3D) simulations at thousands of GHz.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.