Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.     

A novel process variation immune dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z$$^{}$$FET) based on transition metals

Transition metal (TM) electrodes based dopingless zero sub-threshold slope and zero impact ionization FET (DL-Z\(^{2}\)FET) is reported in this paper. The work-function engineering of TM electrodes is used for charge plasma based electrostatic pseudo doping. Work-function difference between TM electrodes and the undoped silicon film induces p\(^{+}\) and n\(^{+}\) regions in the film. TMs exhibit easy tunability of work-function and their CMOS fabrication compatibility pledges for their potential applications as these electrodes. A technology computer-aided design simulation study is performed to provide physical insight into its working mechanism and performance. It exhibits all the inherent characteristics of conventional Z\(^{2}\)FET, viz. zero slope switching, high \(I_{ON}/I_{OFF}\) ratio, lower operating voltages, immunity towards hot electron degradation and gate controlled hysteresis. The detrimental doping control issues, mobility degradation due to heavy doping and statistical random dopant fluctuations can no more obviate the device performance, it results in more process variations immune design. Hence it can be a potential fast switching transistor.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Design and analysis of a gate-all-around CNTFET-based SRAM cell

This paper proposes a highly stable and low power 6-T static random access memory (SRAM) cell design using a gate-all-around carbon nanotube field effect transistor (GAA-CNTFET). The 6-T SRAM cell is designed and analyzed in HSPICE for different performance metrics viz. SNM, read SNM, write SNM, delay, and leakage power for both the top gate CNTFET and the GAA-CNTFET. The effect of variation of the power supply voltage on the leakage current is also presented, and it was found that the GAA-CNTFET accounts for low power dissipation at higher supply voltage. The 6-T SRAM cell is analyzed for different flat band conditions of the p-type CNTFET taking flatband of the n-type as constant, which is called a dual flat band voltage technique. Through simulations, it is found that by increasing the flatband voltage of a p-type CNTFET, the SRAM gives better performance. The dual flatband variation technique is compared with dual chirality technique, and it is observed that both techniques give the same results.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

Investigation of trigate JLT with dual-<Emphasis Type="Italic">k</Emphasis> sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Cross-point memory design challenges and survey of selector device characteristics

In this survey, the design challenges of cross-point memory arrays with emerging nonvolatile memory technologies are discussed. In particular, the write/read scheme for cross-point memory and the associated problems such as voltage drop along interconnect and sneak path current via unselected cells are analyzed. The write voltage margin and power consumption, as well as the read-current sensing margin and latency, are simulated with a voltage-mode sense amplifier for different array sizes and nonlinearity of the selector devices. Finally, state-of-the-art performance and mechanism of selector devices are summarized and they are classified as Type I selector with exponential current–voltage (I–V) characteristics and Type II selector with threshold I–V characteristics. Design challenges and device engineering guidelines are discussed for both types of selector in the summary.     

A novel high-performance H-gate U-channel junctionless FET

A novel high-performance H-shape-gate U-shape-channel junctionless FET (HGUC JL FET) is proposed. Compared with the saddle junctionless FET, the proposed HGUC JL FET shows better subthreshold characteristics and higher on-current. Its electrical properties were extensively investigated by studying the influence of variation of design parameters such as the H-gate thickness, the source/drain extension region height, and the gate oxide thickness and material. Compared with conventional structures, the proposed HGUC JL FET shows better performance, especially on scaling down to several nanometers. The reverse leakage current is also effectively restrained and the \({I}_{\mathrm{on}}\)/\({I}_{\mathrm{off}}\) ratio greatly improved through design optimization.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Double aperture double-gate vertical high-electron-mobility transistor

In this paper, we propose a double aperture double-gate AlGaN/GaN vertical high-electron-mobility transistor (HEMT) to improve the device characteristics, such as the current and the ON resistance (\(\hbox {\textit{R}}_{\mathrm{ON}}\)). The proposed vertical HEMT results are compared to the conventional single aperture single-gate vertical HEMT of equal dimensions, and increased drain current and lower \(\hbox {\textit{R}}_{\mathrm{ON}}\) are shown. A comprehensive simulation study has also been carried out for the proposed device, to analyse the impact of thickness and doping concentration of aperture, drift region, and current blocking layer. In addition, the effect of different materials in current blocking layer on device characteristics is also studied. The obtained results and their effect on device characteristics have been thoroughly analysed and explained accordingly.     

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.     

An impact of bias and structure dependent L_\mathrm{SD} variation on the performance of GaN HEMTs based biosensor

In this paper, we discussed the effect of different bias and structures in relation to S-D distance variation on the device electrical and expected biosensing performance. Devices with source to drain length ( \(L_{SD})\) variations from 3.5, 5.0, 8.0, 14.0, 26.0 to \(52~\upmu \) m were simulated at low and high bias voltages. Different structures having gate recess and finger variations were investigated for the complete range of \(L_{SD}\) variations. Small and very large \(L_{SD}\) variations in non-recessed structure showed good values of drain current \((I_{ds})\) and transconductances \((g_{m})\) at different low and high bias voltages respectively. Therefore expected response time and sensitivity could be improved by choosing a proper bias condition for different biosensing \(L_{SD}\) lengths. A gate recess structure showed better \(g_{m}\) values at low bias conditions for all \(L_{SD}\) lengths. However, \(I_{ds}\) degraded for these structures and hence the expected response time. The non-recessed structure variations in terms of number of fingers and gate width did not change the effective trends in \(L_{SD}\) variation.     

Quantum analysis based extraction of frequency dependent intrinsic and extrinsic parameters for GEWE-SiNW MOSFET

This paper examines the bias-independent and bias-dependent extrinsic and intrinsic parameters of the gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) metal–oxide–semiconductor field-effect transistor (MOSFET) by considering quantum effects. The results reveal that the effect of extrinsic parameters such as the resistance, capacitance, and inductance of the electrodes is less pronounced in the GEWE-SiNW compared with the conventional SiNW or conventional MOSFET. The intrinsic transconductance of the GEWE-SiNW device can be further improved by tuning the gate metal workfunction difference, which results in shorter time constant and lower parasitic capacitance, making it suitable for radiofrequency integrated circuit (RFIC) design. It is also observed that, in the saturation region, the device exhibits improved transconductance and noticeable reduction in \(C_{\mathrm{sdx}}\) [due to drain-induced barrier lowering (DIBL)] but the parasitic capacitance and time constant also reduce. In addition, a non-quasi-static small-signal model has been studied in terms of Z and Y parameters; the results show good agreement with the results of three-dimensional (3D) simulations at thousands of GHz.     

Modeling the performance characteristics of ZnO-based heterojunction photodetectors

We propose and experimentally validate a theoretical closed-form modeling procedure for ZnO-based heterojunction ultraviolet (UV) photodetectors. To do so, we first employ a deposition and growth method based on chemical bath deposition for a typical ZnO/CuO n–p heterojunction structure. The UV detection performance of this type of detector has been examined and confirmed previously. The fabricated device was then tested, and its performance analyzed. We model the performance of the detector by extension of previously proposed analytical models and study the performance of the device. The results show good agreement between the measurements and theoretical modeling.     

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (R_ON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit \( \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) \) are 1140 V, 0.587 mΩ cm² (V_GS = 15 V, V_DS = 1 V), and 2.214 GW/cm², respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).