The effect of sharp-corner emendation of irregular FinFETs on electrothermal characteristics

The present study is an attempt to investigate the impacts of channel modification and the capabilities of amended sharp-corner FinFETs from thermal and electrical points of view. It also provides a new definition for gate-oxide and channel capacitance of irregular fin shape by replacing the contribution of each area in the total gate capacitance expression of the square FinFET. This definition determines the subthreshold reliability of the amended sharp-corner FinFETs. As a function of gate insulator capacitance, channel capacitance, depletion charge per unit length, and fin area, mobile electron concentrations are derived for amended sharp-corner FETs by assuming an arbitrary channel potential profile to simplify the formulation. The comparison results demonstrate that an amended FinFET with a partial cylindrical shape at the top region of fin (PC-FinFET) by higher gate controllability adjusts the hot carrier effects, reduces DIBL, improves the subthreshold characteristics as well as short-channel effects, while the amended-channel FinFET with extended round-bottom region reduces the self-heating effects, attenuates the thermal resistance, and moderates the thermal dependence of electrical characteristics. Therefore, it is deduced that modified-channel FinFET (MC-FinFET), with both cylindrical top and extended bottom regions, has improved thermal and electrical stabilities in both subthreshold and saturation modes in comparison with a conventional thin-film FinFET. The superiority of the MC-FinFET, which was evaluated with three-dimensional simulations, demonstrates the ability of this structure as a high-performance device over the other eliminated sharp-corner FinFETs.     

Fully 3D self-consistent quantum transport simulation of Double-gate and Tri-gate 10 nm FinFETs

We utilize a fully self-consistent 3D quantum mechanical simulator based on the Contact Block Reduction (CBR) method to investigate the effects of fin height and unintentional dopant on the device characteristics of a 10-nm FinFET device. The per-fin height off-current is found to be relatively insensitive to fin height while the corresponding per fin height on-current may significantly depend on fin height due to the stronger confinement with decreasing fin height. Also gate leakage is found to show similar behavior as device on-current with decreasing fin height. Tri-gate (TG) FinFET is found to show better performance compared to Double-gate (DG) FinFET, with the exception of gate leakage current. Simulation results show that an unintentional dopant within the channel can significantly alter device characteristics depending on its position and applied biases. In addition, the effects of unintentional dopant are found to be stronger at high drain bias than at low drain bias.     

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D-V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.     

RF modeling of 40‐nm SOI triple‐gate FinFET

These last years, the triple‐gate fin field‐effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal‐oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three‐dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double‐gate metal‐oxide‐semiconductor field‐effect transistor (symmetric doped double‐gate MOSFET) to reproduce the experimental dc and RF behaviors for 40‐nm technology node Silicon‐on‐Insulator triple‐gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small‐signal behavior, the current gain, and the maximum available power gain cut‐off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Copyright © 2014 John Wiley & Sons, Ltd.     

Monte Carlo simulation of nanoelectronic devices

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.     

Comparison of Double-Gate MOSFETs and FinFETs with Monte Carlo Simulation

A full-band Monte Carlo simulator has been used to analyze and compare the performance of n-channel double-gate MOSFETs and FinFETs. Size quantization effects were accounted for by using a quantum correction based on Schrödinger equation. FinFETs are a variation of typical double-gate devices with the gate surrounding the channel on three sides. From our simulations, we observed that the quantization effects in double-gate devices are less significant as compared to bulk MOSFETs. The total sheet charge density drops only slightly as the depletion of charge at the interface is counterbalanced by the increased volume inversion effect. We also observed an appreciable drop in average velocity distribution when quantum corrections were applied. For FinFETs, the fin extension lengths on either side of the gate affect the device performance significantly. These underlap regions have low carrier concentration and behave as large resistors. The current drops non-linearly with increasing fin extension lengths.     

Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.     

Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

Scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale regime. Memories occupy a major portion of chip area. Their reliability is a primary concern in harsh environments such as cosmic radiation. Also, in the nanoscale regime, reliability proves to be challenging. We present herein FinFET- and junctionless FinFET-based 6T-static random-access memories (SRAMs) for the 16-nm technology node. In the literature so far, either drain or gate strike has been considered. In this work, we studied irradiation in both the drain and the gate region. The FinFET-based 6T-SRAM showed higher hardness to single-event upset (SEU) radiation in both regions compared to junctionless FinFET-based 6T-SRAM.     

Self-consistent treatment of quantum transport in 10 nm FinFET using Contact Block Reduction (CBR) method

A fully quantum mechanical approach must be utilized to investigate the characteristics of nanoscale semiconductor devices and capture the essential physics with high accuracy. In this work a very efficient quantum mechanical transport simulator based on Contact Block Reduction (CBR) method is used to analyze the behavior of 10 nm FinFET device in the quasi-ballistic regime of operation. Simulation results depict the transformation of multiple channels into a single merged channel across the fin as the fin width is reduced gradually. Also we observe that short channel effects can be minimized by reducing the fin thickness, which is evident from the device transfer characteristics for different fin thickness presented in this paper. A comparison of simulation results with the available experimental data is presented. An optimized 10 nm gate length FinFET structure is suggested.     

Bias and geometry optimization of FinFET for RF stability performance

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f _k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.     

A systematic investigation of the integrated effects of gate underlapping,dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of \(\mathrm{SiO}_{2}\) as the gate dielectric. Therefore, a hetero gate dielectric \(\mathrm{SiO}_{2}\) on the drain side and \(\mathrm{HfO}_{2}\) on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

NMOSFET ESD self-protection strategy and underlying failuremechanism in advanced 0.13-μm CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L_npn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I_t2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device     

Low-Frequency Noise-Based Degradation Prediction of$hboxAl_xhboxGa_1 - xhboxN/GaN$MODFETs

Degradation prediction of AlGaN/GaN MODFET is explored based on characterization of gate and drain low- frequency noise. Heterostructures grown by molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) are used for this purpose. Devices from the former category were unpassivated while those of the latter were passivated. Despite the highly variable gate noise current characteristics among unpassivated MBE devices and between MBE and MOCVD-based devices, it is demonstrated that the drain noise current characteristics of the two groups of devices have considerable resemblance. Moreover, it is shown that the drain noise current level can be used as a means for gate degradation prediction     

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Numerical Analysis of Coaxial Double Gate Schottky Barrier Carbon Nanotube Field Effect Transistors

Carbon nanotube field-effect transistors (CNTFETs) have been studied in recent years as a potential alternative to CMOS devices, because of the capability of ballistic transport. The ambipolar behavior of Schottky barrier CNTFETs limits the performance of these devices. A double gate design is proposed to suppress this behavior. In this structure the first gate located near the source contact controls carrier injection and the second gate located near the drain contact suppresses parasitic carrier injection. To avoid the ambipolar behavior it is necessary that the voltage of the second gate is higher or at least equal to the drain voltage. The behavior of these devices has been studied by solving the coupled Schrödinger-Poisson equation system. We investigated the effect of the second gate voltage on the performance of the device and finally the advantages and disadvantages of these options are discussed.     

Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices?

We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.     

Modeling of FinFET: 3D MC Simulation Using FMM and Unintentional Doping Effects on Device Operation

Novel device concepts such as dual gate SOI, Ultra thin body SOI, FinFETs, etc., have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. These novel devices suppress some of the Short Channel Effects (SCE) efficiently, but at the same time more physics based modeling is required to investigate device operation. In this paper, we use semi-classical 3D Monte Carlo device simulator to investigate important issues in the operation of FinFETs. Fast Multipole Method (FMM) has been integrated with the EMC scheme to replace the time consuming Poisson equation solver. Effect of unintentional doping for different device dimensions has been investigated. Impurities at the source side of the channel have most significant impact on the device performance.     

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.