Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

Double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with GaN channel material are very promising for use in future high-performance low-power nanoscale device applications. In this work, GaN-based sub-10-nm DG-MOSFETs with different gate work function, \(\varPhi \), were designed and their performance evaluated. Short-channel effects (SCEs) were significantly reduced by introduction of gates made of dual metals. Use of gold at the source side, having higher \(\varPhi \) (\(\varPhi _{\mathrm{Au}}=5.11\,\hbox {eV}\)) compared with aluminum (\(\varPhi _{\mathrm{Al}}=4.53\,\hbox {eV}\)), at the drain side enhanced the gate control over the channel and screened the effect of the drain on the channel. Dual-metal (DM) DG-MOSFETs showed better results in the nanoscale regime and were more robust to SCEs. Therefore, GaN-based sub-10-nm DM DG-MOSFETs are suitable candidates for use in future complementary metal–oxide–semiconductor (CMOS) technology.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.     

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage (\(V_\mathrm{TG}\)) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson’s equation in the lightly doped Si film and employing the physical definition of \(V_\mathrm{TG}\). A numerical simulation study of the transfer characteristics and \(V_\mathrm{TG}\) of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of \(V_\mathrm{TG}\) is performed based on the transconductance change method as already used for conventional metal–oxide–semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on \(V_\mathrm{TG}\) are reported. The dependence of \(V_\mathrm{TG}\) on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.     

Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance

In this paper, we aim to explore the potential benefits of using source side only dual-k spacer (Dual-kS) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low power operation at 20 nm gate length. It has been observed from the results that Dual-kS (inner spacer high-k) FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source side and results into improvement in transconductance \((g_{m})\) and output conductance \((g_{ds})\). It was also found that drain side only dual-k spacer (Dual-kD) improves the coupling of the gate fringe field to the underlap region towards the drain side which helps to shift away the drain field from gate edge and results into improvement in output conductance \((g_{ds})\) only at the cost of increase in Miller capacitance. A comparative simulation study has been performed on four different device structures namely both side low-k spacers (conventional), both side dual-k spacer (Dual-kB), Dual-kD and Dual-kS structures. From the simulation study, it was found that that Dual-kS structure has potential to improve \(g_{m}\) by \(\sim \)8.7 %, \(g_{ds}\) by \(\sim \)32.24 %, intrinsic gain \((A_{V0})\) by \(\sim \)11.44 %, early voltage \((V_{EA})\) by \(\sim \)47.59 %, maximum oscillation frequency (\(f_{MAX}\)) by \(\sim \)1.7 % and the ratio of gate-source capacitance and gate-drain capacitance \((C_{gs}/C_{gd})\) by \(\sim \)15.27 % with a slight reduction in the value of unity gain cut-off frequency (\(f_{T}\)) by \(\sim \)0.58 % in comparison to the conventional structure at drain current \((I_{ds})\) of \(10\,\upmu \)A/\(\upmu \)m. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on Dual-kS FinFET structure.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

Investigation of trigate JLT with dual-<Emphasis Type="Italic">k</Emphasis> sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.     

Optimal design of the multiple-apertures-GaN-based vertical HEMTs with $$\hbox {SiO}_{2}$$ current blocking layer

Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide \((\hbox {SiO}_{2})\) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with \(\hbox {SiO}_{2}\) CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with \(0.5\hbox {-}\upmu \hbox {m}\)-thick \(\hbox {SiO}_{2}\) layer and \(1\hbox {-}\upmu \hbox {m}\)-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at \(\hbox {V}_\mathrm{G}= 1\,\hbox {V}\) and \(\hbox {V}_\mathrm{D}= 30\,\hbox {V}\), and the breakdown voltage of 480 V have been achieved for the optimized device.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Series and parallel resistance effects on the C–V and G–V characteristics of $$\mathrm{Al}/\mathrm{SiO}_{2}$$/Si structure

This paper investigates the electrical behavior of the C–V and G–V characteristics of \(\mathrm{Al}/\mathrm{SiO}_{2}/\mathrm{Si}\) structure. The modeling of capacitance and conductance has been developed from complex admittance treatment applied to the proposed equivalent circuit. Poisson transport equations have been used to determine the charge density, surface potential, total capacitance, and flatband and threshold voltages as a function of the gate voltage, frequency (\(\omega )\), and series \(({R}_{\mathrm{s}})\) and parallel \(({R}_{\mathrm{p}})\) resistances. Results showed a frequency dispersion of C–V and G–V curves in both accumulation and inversion regimes. With increasing frequency, the accumulation capacitance is decreased, whereas the conductance is strongly increased. The shape, dispersion, and degradation of C–V and G–V characteristics are more influenced when parallel and series resistances \((\mathrm{R}_{\mathrm{s}}\), \(\mathrm{R}_{\mathrm{p}})\) are dependent to substrate doping density. The variation of \(\mathrm{R}_{\mathrm{s}}\) and \(\mathrm{R}_{\mathrm{p}}\) values led to a reduction of flatband voltage from ?1.40 to ?1.26 V and increase of the threshold voltage negatively from ?0.28 to ?0.74 V. A good agreement has been observed between simulated and measured C–V and G–V curves obtained at high frequency.     

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.     

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron’s and hole’s clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance \((\hbox {g}_\mathrm{m})\), transconductance to drain current ratio \((\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})\), output-conductance (g\(_{d})\), output resistance \((\hbox {r}_\mathrm{d})\), early voltage \((\hbox {V}_\mathrm{EA})\), intrinsic gain \((\hbox {A}_\mathrm{V})\), total gate capacitance \((\hbox {C}_\mathrm{gg})\) and unity gain frequency \((\hbox {f}_\mathrm{T})\). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.     

Filament-to-dielectric band alignments in $$\hbox {TiO}_{2}$$ and $$\hbox {HfO}_{2}$$HfO2 resistive RAMs

The next-generation nonvolatile memory storage may well be based on resistive random access memories (RRAMs). \(\hbox {TiO}_{2}\) and \(\hbox {HfO}_{2}\) have been widely used as the resistive switching layer for RRAM devices. However, the electronic properties of the filament-to-dielectric interfaces are still not well understood yet, compared to those of the electrodes and the dielectric. In this work, we study the electronic structures of three typical filament and dielectric structures, \(\hbox {Ti}_{4}\hbox {O}_{7}/\hbox {TiO}_{2}\), \(\hbox {Hf}_{2}\hbox {O}_{3}/\hbox {HfO}_{2}\) and \(\hbox {Hf}/\hbox {HfO}_{2}\), using ab initio calculations. We implement the GGA-1/2 method, which rectifies the band gaps of GGA through self-energy correction. Our calculation predicts an ohmic contact for the \(\hbox {Ti}_{4}\hbox {O}_{7}/\hbox {TiO}_{2}\) interface, where the defective \(\hbox {Ti}_{4}\hbox {O}_{7}\) phase was experimentally identified as the filament composition in \(\hbox {TiO}_{2}\). However, there is a finite Schottky barrier existing in either \(\hbox {Hf}_{2}\hbox {O}_{3}/\hbox {HfO}_{2}\) interface (1.96 eV) or \(\hbox {Hf}/\hbox {HfO}_{2}\) interface (0.61 eV), the two probable filament–dielectric configurations in hafnia-based RRAM. Our results suggest that the distinct filament-to-dielectric band alignments in \(\hbox {TiO}_{x}\) and \(\hbox {HfO}_{x}\) systems account for the much larger resistance window for the latter.     

20-nm T-gate composite channel enhancement-mode metamorphic HEMT on GaAs substrates for future THz applications

In this paper, the RF and DC behaviours of a SiN-passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with \({\updelta }\)-doped sheets on either side of the composite channel are studied using the Synopsys TCAD tool. The 20-nm enhancement-mode MHEMT with \({\updelta }\)-doped sheets on either side of the \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\)/InAs/ \(\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}\) multilayer channel shows a transconductance of 3000 mS/mm, cut-off frequency (\({f}_{\mathrm{T}}\)) of 760 GHz and a maximum-oscillation frequency (\({f}_{\mathrm{max}}\)) of 1270 GHz. The threshold voltage of the device is found to be 0.07 V. The room-temperature Hall mobilities of the two-dimensional sheet charge density (2DEG) are measured to be over \(12800\,\hbox {cm}^{2}\)/Vs with a sheet charge density larger than 4 \(\times \) \(10^{12}\,\hbox {cm}^{-2}\). These high-performance enhancement-mode MHEMTs are attractive candidates for future terahertz applications such as high-resolution radars for space research and also for low-noise wide-bandwidth amplifier for future communication systems.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Simulation of dielectric behavior in RFeO$$_{}$$ orthoferrite ceramics (R = rare earth metals)

Due to their colossal dielectric constant (CDC), \(\hbox {RFeO}_{3}\), orthoferrite ceramics (R = rare earth metal) have recently attracted much attention. In the present research, the dielectric constants of \(\hbox {RFeO}_{3}\) orthoferrite ceramics, whether with or without CDC, have been simulated. The type of synthesis method, the type of R material, temperature, and frequency as the effective parameters on the dielectric behavior are introduced to the model. Another input parameter is the ratio of \(\hbox {Fe}^{+2}/\hbox {Fe}^{+3}\) peak area (in the XPS diagram), which is the most important parameter that affects the CDC behavior. Initially, a colossal database is formed by means of WebPlotDigitizer software and 2930 experimental data, and then the simulation is carried out through gene expression programming. Two case studies are also performed on \(\hbox {PrFeO}_{3}\) and \(\hbox {NdFeO}_{3}\) orthoferrite ceramics to validate the accuracy of the presented model. \(\hbox {PrFeO}_{3}\) exhibits significant CDC behavior whereas the \(\hbox {NdFeO}_{3}\) ceramic samples possess little CDC property, both of which were precisely simulated by the model. Two-dimensional tenth-degree equations resulting from the model predict the dielectric constant variations accurately.     

Structural,electrical and optical properties of $$\hbox {InGaZnO}_{4}$$ and $$\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}$$In29Sn3O48: a first-principles study

First-principles calculations were performed to investigate the electrical and optical properties of \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) with Sn-doped \(\hbox {In}_{2}\hbox {O}_{3}\) and \(\hbox {InGaZnO}_{4}\) (IGZO). The band structure, density of states, optical properties including dielectric function, loss function, reflectivity and absorption coefficient are calculated. The calculated total energy shows that the most stable crystal structures are type III for \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) and type II for \(\hbox {InGaZnO}_{4}\). The band structure indicates the both \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) and \(\hbox {InGaZnO}_{4}\) are direct gap semiconductors. The intrinsic band gap of \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) is much narrower than that of \(\hbox {InGaZnO}_{4}\), and results in a better electrical conductivity for \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\). The density of states shows the main hybridization occurring between In-4d and O-2p states for \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) while between In-4d In-5p, Zn-4s and O-2p states for \(\hbox {InGaZnO}_{4}\) near the valence band maximum. The reflectivity index \(R({\omega })\) shows that the peak value of \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) and \(\hbox {InGaZnO}_{4}\) appears only in the ultraviolet range, indicating that these two materials have all excellent transparency. In addition, the absorption coefficient \({\alpha }({\omega })\) of both \(\hbox {In}_{29}\hbox {Sn}_{3}\hbox {O}_{48}\) and \(\hbox {InGaZnO}_{4}\) is high in the ultraviolet frequency range, and therefore they show, a high UV absorption rate.     

First-principle calculations of electronic and ferromagnetic properties of $$\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}$$

We have used the first-principle calculations of density functional theory within full-potential linearized augmented plane-wave method to investigate the electronic and ferromagnetic properties of \(\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}\) alloys. The electronic structures of \(\hbox {Al}_{0.25}\hbox {V}_{0.75}\hbox {Sb}, \hbox {Al}_{0.5}\hbox {V}_{0.5}\hbox {Sb}\) and \(\hbox {Al}_{0.75}\hbox {V}_{0.25}\hbox {Sb}\) exhibit a half-metallic ferromagnetic character with spin polarization of 100 %. The total magnetic moment per V atom for each compound is integral Bohr magneton of 2 \(\mu _{\mathrm{B}}\), confirming the half-metallic feature of \(\hbox {Al}_{1-x}\hbox {V}_{x}\hbox {Sb}\). Therefore, these materials are half-metallic ferromagnets useful for possible spintronics applications.     

Computational study of a new resonant tunneling diode based on an $$\hbox {MoS}_{2}$$ nanoribbon with sulfur line vacancies

Recent experimental studies have shown that sulfur vacancies in monolayer \(\hbox {MoS}_{2}\) are mobile under exposure to an electron beam and tend to accumulate as sulfur line vacancies (Komsa in Phys Rev B 88: 035301, 2013). In this work, we designed a new resonant tunneling diode (RTD) based on this natural property. Two rows of sulfur vacancies are introduced into armchair \(\hbox {MoS}_{2}\) nanoribbons (\(\hbox {A-MoS}_{2}\) NRs) to tune the nanoribbons’ bandgap to obtain the double-barrier quantum well structure of the resonant tunneling diode. This arrangement has a unique benefit that will result in very little physical distortion. A tight-binding (TB) model, with five 4d-orbitals of the Mo atom and three 3p-orbitals of the S atom, is employed for calculations. In the TB model, which is described in terms of Slater–Koster parameters, we also incorporate the changes of edge bonds. Density functional theory is used to determine all the necessary parameters of the TB model. They are obtained by an optimization procedure which achieves very fine parameter values, which can regenerate the most important energy bands of \(\hbox {A-MoS}_{2}\) NRs of different widths, with highly satisfactory precision. The introduction of these new parameters is another contribution of this work. Lastly, the nonequilibrium Green’s function formalism based on the TB approximation is used to explore the properties of the new RTD structures based on \(\hbox {A-MoS}_{2}\) NRs. Negative differential resistance with peak to valley ratio (PVR) of about 78 at room temperature is achieved for one RTD, having peak current \(I_\mathrm{p}=90\) nA. We show that the PVR can exceed 120 when increasing the barrier length of the RTD at the expense of lower \(I_\mathrm{p}\).     

Transport studies of $$\hbox {CeO}_{2}$$ molecular device and adsorption behavior of CO on $$\hbox {CeO}_{2}$$ device: a first-principles investigation

Using density functional theory and the non-equilibrium Green’s function formalism, the transport and CO adsorption properties of \(\hbox {CeO}_{2}\) molecular device are studied. The band structure shows that \(\hbox {CeO}_{2}\) nanostructure exhibits semiconducting nature. The electron density is found to be more in oxygen sites rather than in cerium sites along \(\hbox {CeO}_{2}\) nanostructure. The density of states spectrum shows the variation in density of charge upon adsorption of CO on CeO\(_2\) device. The transmission spectrum provides the insights on the transition of charge in \(\hbox {CeO}_{2}\) molecular device upon adsorption of CO along the scattering region. I–V characteristics confirm the adsorption of CO with the variation of current along \(\hbox {CeO}_{2}\) molecular device. The findings show that \(\hbox {CeO}_{2}\) two probe molecular device can be efficiently used for CO detection in the atmosphere.