Bias and geometry optimization of FinFET for RF stability performance

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f _k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.     

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.     

Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

结构稀疏通道先验盲图像去模糊方法

针对盲图像去模糊过程中主结构不准确和边缘不清晰问题,提出了一种结构稀疏通道先验(SSCP)盲图像去模糊方法。SSCP表示模糊图像比清晰图像具有更少结构稀疏通道的先验方法。利用SSCP的性能特性,将其作为新的正则化项引入经典去模糊模型,构建盲去模糊新模型,实现对模糊核的准确估计。通过坐标下降法,交替优化求解潜像与模糊核变量。最后,通过反卷积得到去模糊的清晰复原图像,在基准数据集和自然状态模糊图像上开展主观和客观对比实验,并进行人脸和低亮度真实模糊图像的应用拓展实验。实验结果表明,提出的方法在模糊去除、结构恢复、边缘保留和视觉效果方面的性能比经典去模糊方法平均提高了1.72%,通过该方法设计出的计算装置能够实现机器视觉领域中模糊图像的高精度清晰化处理。     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

基于DSP的ADC测试功耗优化设计

随着大规模混合信号集成电路设计水平及复杂性的不断提高,对其进行测试的难度与成本变得越来越高,而测试功耗过高已经成为影响测试成本的一个重要因素。ADC作为混合信号电路的典型代表,已经应用在了各种集成模块上。文章中为降低ADC测试功耗,对ADC的测试结构进行了部分改进,并运用遗传算法搜索了低功耗测试激励。理论研究及仿真实验表明,优化后的结构和低功耗测试激励较优化前能同时降低测试时的峰值功耗和平均功耗。     

旋流排沙渠道体型优化的正交数值试验方法和应用

为优化多泥沙河流引水渠道内的泥沙级配,实现泥沙分选的效果,提出了一种新型旋流排沙渠道。基于数值模拟与模型试验结果,采用正交数值试验方法,以分流比与排沙洞典型断面的流速为目标函数,优化了旋流排沙渠道的关键体型参数,对比分析了体型优化前后旋流排沙渠道的水沙特性。结果表明,正交数值试验设计能有效提升结构的优化效率,获得具有良好性能的旋流排沙渠道。当渠道来流量为30 L·s^-1时,优化体型的排沙耗水量较原体型减小21.5%,分流比减小4.6%,排沙洞出口断面最大流速增大10.8%,水流的挟沙能力增强,在排沙洞内形成更有利于泥沙运动的旋转水流条件;体型优化前后的旋流排沙渠道对粒径为0.075～3.0 mm泥沙的总体截沙率分别高达90%和88%,表明旋流排沙渠道具有良好的排沙特性,且优化体型排沙洞内的泥沙淤积量较原体型减小61.8%。本成果可为这种新型旋流排沙渠道体型优化和其在引水渠道等工程中的应用提供参考。     

3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum correction

The performance of FinFET and FDSOI devices is compared by 3D Monte Carlo simulation using an enhanced quantum correction scheme. This scheme has two new features: (i) the quantum correction is extracted from a 2D cross-section of the 3D device and (ii) in addition to using a modified oxide permittivity and a modified work function in subthreshold, the work function is ramped above threshold to a different value in the on-state. This approach improves the accuracy of the quantum-correction for multi-gate devices and is shown to accurately reproduce 3D density-gradient simulation also at short channel lengths. 15 nm FDSOI device performance with thin box and back-gate bias is found to be competitive: compared to a FinFET with (110)/〈110〉 sidewall/channel orientation, the on-current for N-type devices is 25 % higher and the off-current is only increased by a factor of 2.5.     

Optimization of saddle junctionless FETs for extreme high integration

In this work, a saddle junctionless field effect transistors with optimal gate structure is proposed for extreme high integration. The forward and reverse I–V characteristics of the optimal saddle JL FETs have been extensively investigated by analyzing the influence of doping concentration, the height of the source/drain extension region and the gate structure engineering from physical insight. Design optimization has also been performed and the optimal parameters have been proposed.     

Microscopic simulation of RF noise in junctionless nanowire transistors

A deterministic solver for the analysis of microscopic noise and small-signal fluctuations in junctionless nanowire field-effect transistors is presented, which is based on a self-consistent and simultaneous solution of the Poisson/Schrödinger/Boltzmann equations. It is verified that the numerical framework fulfills the vital properties of reciprocity and passivity in the small-signal sense, and yields Johnson–Nyquist noise under equilibrium conditions. Key figures such as the cutoff frequency, drain excess noise factor, the Fano factor, and gate/drain correlation coefficient are presented at various bias conditions. In this work we show that similar to the inversion-mode MOSFETs, the gate and drain current noises mainly stem from the warm electrons at the source side, whereas the hot electrons do not have a significant contribution. Also, our results show that the device behaves similar to long-channel FETs in terms of its excess noise even for a channel length of 10 nm, due to the strong control of its electrostatics by the all-around gate.     

A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance

Over the years, the approach of cylindrical gate MOSFETs has attracted several research initiatives due to the very inherent benefit of the cylindrical geometry over other conventional planar structures. Nowadays, the present boon in the research field of nanoscale device physics is attributed to a large extent by the development of junctionless devices. In our current research endeavor, we have for the first time proposed a new idea by incorporating the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless cylindrical gate MOS structure, thereby presenting a new device structure, a junctionless work function engineered gate cylindrical gate MOSFET (JL WFEG CG MOSFET). We have presented a rigorous analytical modeling of the proposed JL WFEG CG MOS structure by solving the two dimensional Poisson’s equation in cylindrical co-ordinates. Based on this analytical modeling, an overall performance comparison of the proposed JL WFEG CG MOS and normal JL CG MOS structure has been investigated in order to testify the improved performance of the proposed JL WFEG CG structure over its normal JL CG equivalent in terms of reduced short channel effects, threshold voltage roll off, drain induced barrier lowering and superior current driving capability. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

小型轴流式吹风机结构优化设计研究

吹风机的设计综合了多种结构关系,其试验设计过程缺少规律性,设计成本较高.吹风机的结构设计参数决定其工作性能,采用计算流体力学的方法,分析风扇和马达轴向距离、风扇和风筒间隙以及风筒的轴向长度三种不同参数对吹风机出口风速的影响规律.在单因素分析的基础上进行Box-Behnken试验设计,引用响应面分析法求回归方程,以出口风速最高为优化目标,得到吹风机性能最优的结构参数.     

Design and optimization of electrostatic fluid accelerators

Electrostatic air propulsion is a promising technology with such potential applications as energy-efficient ventilation, air sterilization, cooling of electronics, and dehumidification. The challenges of existing designs include the need to increase air speed, backpressure, energy efficiency, and heat exchange capability. The ultimate goal of this direction of research is to create multi-channel energy efficient ionic pumps. In the described project, a single cell analysis is conducted in this study as a building block of future designs. This paper presents the numerical simulation and experimental results of electrostatic fluid accelerators. This study was conducted for the purpose of optimizing device characteristics through the control of the electric field distribution. Simulations were performed for multiple collector electrode voltage distributions. A method to quantify the change in pump performance between different voltage distributions is presented. The influence of space charge on pump performance is also discussed. A significant improvement of air velocity generated by optimized electrostatic fluid accelerators has been achieved using the proposed approach.