二维离散小波变换的FPGA实现

提出了一种二维离散小波变换的FPGA实现方法,并对设计结果进行了功能和时序仿真。本设计方案不仅可以满足实时性的要求,而且采用模块化设计,可以实现多级小波变换。     

二维实值离散Gabor变换时间递归算法的双层并行格型结构实现方法

本文首先简单回顾了作者曾提出的二维实值离散Gabor变换及其与复值离散Gabor变换的简单关系，然后着重探讨了二维实值离散Gabor变换快速计算问题，提出了二维实值离散Gabor变换系数求解的时间递归算法以及由变换系数重构原图像的块时间递归算法，研究了双层并行格型结构实现算法的方法，计算复杂性分析及与其它算法的比较证明了双层并行格型结构实现方法在实时处理方面的优越性。     

An efficient VLSI architecture for 2-D wavelet image coding withnovel image scan

A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line     

Multirate-based fast parallel algorithms for 2-D DHT-based real-valued discrete Gabor transform

Novel algorithms for the multirate and fast parallel implementation of the 2-D discrete Hartley transform (DHT)-based real-valued discrete Gabor transform (RDGT) and its inverse transform are presented in this paper. A 2-D multirate-based analysis convolver bank is designed for the 2-D RDGT, and a 2-D multirate-based synthesis convolver bank is designed for the 2-D inverse RDGT. The parallel channels in each of the two convolver banks have a unified structure and can apply the 2-D fast DHT algorithm to speed up their computations. The computational complexity of each parallel channel is low and is independent of the Gabor oversampling rate. All the 2-D RDGT coefficients of an image are computed in parallel during the analysis process and can be reconstructed in parallel during the synthesis process. The computational complexity and time of the proposed parallel algorithms are analyzed and compared with those of the existing fastest algorithms for 2-D discrete Gabor transforms. The results indicate that the proposed algorithms are the fastest, which make them attractive for real-time image processing.     

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform

A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size .     

Fast Parallel Approach for 2-D DHT-Based Real-Valued Discrete Gabor Transform

Two-dimensional fast Gabor transform algorithms are useful for real-time applications due to the high computational complexity of the traditional 2-D complex-valued discrete Gabor transform (CDGT). This paper presents two block time-recursive algorithms for 2-D DHT-based real-valued discrete Gabor transform (RDGT) and its inverse transform and develops a fast parallel approach for the implementation of the two algorithms. The computational complexity of the proposed parallel approach is analyzed and compared with that of the existing 2-D CDGT algorithms. The results indicate that the proposed parallel approach is attractive for real time image processing.      

A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Two-dimensional (2-D) convolution is widely used in image and video processing. Although the operation is simple, 2-D convolution is however both computationally expensive and memory-intensive. Field-programmable-gate-array (FPGA)-based parallel processing architectures were proposed to accelerate calculations for 2-D convolution. And data buffers implemented with FPGA on-chip resources were used to avoid direct access to external memories. Full buffering and partial buffering (PB) schemes were adopted in previous works. The former would consume a large amount of FPGA resources, while the latter would cause a sharp increase in external memory bus bandwidth. In this brief, we present a multiwindow PB scheme for FPGA-based 2-D convolvers. Compared with the aforementioned methods, the new buffering strategy exhibits a good balance between on-chip resource utilization and external memory bus bandwidth, and therefore is suitable for low-cost FPGA implementation     

FPGA implementation for 2D discrete wavelet transform

An operator correlation-based algorithm and its VLSI architecture For computing the 2D discrete wavelet transform is presented. The proposed discrete wavelet transform architecture was simulated in Verilog and synthesised with the FPGA compiler. The implementation for the 2D discrete wavelet transform on an FPGA-based design style is described     

基于整数小波的图像处理系统在硬件中的实现

随着互联网的普及和图像应用范围的不断扩大, 对图像的处理提出了新的要求,即不仅要求对图像识别的准确,还要求达到实时处理,因此系统以高性能数字信号处理器ADSP-BF561和大规模现场可编程门阵列(FPGA)作为核心,结合离散整数小波变换,在硬件系统上实现提升方法的整数小波变换和Mallat算法小波变换,取得了较好的试验效果.     

Fast splitting alpha-rooting method of image enhancement: tensor representation.

In the tensor representation, a two-dimensional (2-D) image is represented uniquely by a set of one-dimensional (1-D) signals, so-called splitting-signals, that carry the spectral information of the image at frequency-points of specific sets that cover the whole domain of frequencies. The image enhancement is thus reduced to processing splitting-signals and such process requires a modification of only a few spectral components of the image, for each signal. For instance, the alpha-rooting method of image enhancement can be fulfilled through processing separately a maximum of 3N/2 splitting-signals of an image (N x N), where N is a power of two. In this paper, we propose a fast implementation of the a-rooting method by using one splitting-signal of the tensor representation with respect to the discrete Fourier transform (DFT). The implementation is described in the frequency and spatial domains. As a result, the proposed algorithms for image enhancement use two 1-D N-point DFTs instead of two 2-D N x N-point DFTs in the traditional method of alpha-rooting.     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

A programmable image processing system using FPGAs

Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.     

A Hybrid Compression Method for Integral Images Using Discrete Wavelet Transform and Discrete Cosine Transform

Integral imaging (II) is a promising three-dimensional (3-D) imaging technique that uses an array of diffractive or refractive optical elements to record the 3-D information on a conventional digital sensor. With II, the object information is recorded in the form of an array of subimages, each representing a slightly different perspective of the object In order to obtain high-quality 3-D images, digital sensors with a large number of pixels are required. Consequently, high-quality II involves recording and processing large amounts of data. In this paper, we present a compression method developed for the particular characteristics of the digitally recorded integral image. The compression algorithm is based on a hybrid technique implementing a four-dimensional transform combining the discrete wavelet transform and the discrete cosine transform. The proposed algorithm outperforms the baseline JPEG compression scheme applied to II and a previous compression method developed for II based on MPEG II.     

基于小波域Curvelet变换的湍流图像去噪算法

为了提高湍流图像的空间分辨率,提出了一种基于小波域Curvelet变换(wavelet domain Curvelet transform,WDCT)的湍流图像去噪算法。该算法根据湍流退化图像噪声的统计特性,结合贝叶斯萎缩方法优化阈值选择。首先,对含噪湍流图像进行单层二维离散小波变换,接着提取高频系数并对它作快速离散Curvelet变换,最后根据贝叶斯准则估计阈值T,改进阈值的自适应选取方法,获得最优阈值,最后给出湍流图像去噪实现过程。为验证本文算法,根据客观评价标准峰值信噪比(peak signal to noise ratio,PSNR)和均方根误差(mean square error,MSE),对模拟图像和实测湍流图像进行去噪实验。与DWT-NABayesShrink算法、UWT算法相比,视觉效果更好,PSNR值分别提高7.27%和4.92%,MSE值分别降低26.3%和23.1%。本文算法得到较清晰的目标图像,对湍流退化图像去噪有一定的应用价值。     

基于信息冗余的小波红外图像去噪算法

红外图像具有图像灰度集中、对比度低等特点,因而红外图像增强是红外图像应用必不缺少的部分,随之而来的是图像噪声的放大,为了进一步提高红外图像质量,需对增强后图像去噪。现有众多去噪方法中,极少同时兼顾算法效果及可实现性。提出了一种基于信息冗余的小波去噪算法,此算法在离散小波变化(DWT)过程中分别以不同的下采样方式获取多组含有相似冗余信息的小波系数,再利用噪声估计对小波系数进行非线性变换,抑制高频噪声并保留细节,然后利用变换后小波系数重构(IDWT)多副图像,利用含相似冗余信息的多副图像加权进一步去除高频噪声,获取最终去噪图像。此算法已在单片FPGA中进行实现,利用ALTERA CYCLONIII芯片实现后的处理帧频达到50 fps,满足实时性要求。     

提升小波高速分解的系统设计与实现

为了解决小波变换在图像实时处理系统中的瓶颈问题,提出了一种硬件实现9/7整形小波高速变换的方法。该方法使用新的小波变换结构和小波变换基,采用一种基于行列同时变换的多级同时变换方式,即进行多级同时变换,且每一级的行列变换也同时进行。使用现场可编程逻辑门阵列（FPGA,Field Programmable Gate Array）的IP核实现片内缓存,降低了设计的复杂度,实现了图像的高速分解。整个设计采用VHDL对算法完成建模和实现,综合和仿真结果表明,该系统占用的资源少,分解速度很快,实现了高速的图像数据流输出,可应用到图像压缩的很多领域。     

CCSDS中二维整数小波变换的FPGA实现方法

CCSDS空间图像压缩标准(CCSDS 122.0-B-1)的核心算法之一是三级二维小波变换,此变换适合用可编程逻辑电路实现。文章介绍了整数9/7小波变换的特点,提出了一种基于FPGA的二维变换快速实现结构,该方法利用FPGA内部Block RAM进行行暂存,实现了行列同时变换的效果,节省了内部寄存器资源,并获得了较高的数据吞吐率。在此基础上,文章还给出了两种适用于不同需求的多级变换架构,并通过仿真验证了其合理性。     

基于FPGA的小波图像实时处理方法

基于小波变换的滤波方法应用于红外图像处理中可以在降低噪声的同时提升图像细节,有效改善图像画质.介绍了一种采用FPGA的小波图像处理方法及其硬件处理架构.通过合理有效地进行算法硬件设计,在单片FPGA芯片上实现了图像的实时处理,有利于红外机芯的小型化.     

An Integrated Systolic Array Design for Video Compression

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. These functions are the prime components in video compression and take a great amount of computation. To meet the real-time application requirements, many systolic array architectures are proposed for individually performing one of those functions. However, these functions contain similar computational procedure. The matrix-vector product forms of the three functions are quite analogous. After extracting the common computation component, we design an integrated one-dimensional systolic array that can perform aforementioned three functions. The proposed architecture can efficiently perform three typical functions: (1) the full-search block matching with block of size 16 × 16 and the search are from –8 to 7; (2) the 2-D 2 level Harr transform with block of size 8 × 8; and (3) the full-search vector quantization with input vector of size 2 × 2. A utilization rate of 100% to 97% is achieved in the course of executing full-search block matching and full-search vector quantization. When it comes to perform 2-D discrete wavelet transform, the utilization rate is about 32%. The proposed integrated architecture has lowered hardware cost and reduced hardware structure. It befits the VLSI implementation for video/image compression applications.