Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Tunable electronic transport characteristics of surface-architecture-controlled ZnO nanowire field effect transistors

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.     

SiGe nanowire field effect transistors

Si0.5Geo0.5 nanowires have been utilized to fabricate source-drain channels of p-type field effect transistors (p-FETs). These transistors were fabricated using two methods, focused ion beam (FIB) and electron beam lithography (EBL). The electrical analyses of these devices show field effect transistor characteristics. The boron-doped SiGe p-FETs with a high-k (HfO2) insulator and Pt electrodes, made via FIB produced devices with effective hole mobilities of about 50 cm2V(-1)s(-1). Similar transistors with Ti/Au electrodes made via EBL had effective hole mobilities of about 350 cm2V(-1)s(-1).     

Top-gate ZnO nanowire transistors and integrated circuits with ultrathin self-assembled monolayer gate dielectric

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.     

Printable ion-gel gate dielectrics for low-voltage polymer thin-film transistors on plastic

An important strategy for realizing flexible electronics is to use solution-processable materials that can be directly printed and integrated into high-performance electronic components on plastic. Although examples of functional inks based on metallic, semiconducting and insulating materials have been developed, enhanced printability and performance is still a challenge. Printable high-capacitance dielectrics that serve as gate insulators in organic thin-film transistors are a particular priority. Solid polymer electrolytes (a salt dissolved in a polymer matrix) have been investigated for this purpose, but they suffer from slow polarization response, limiting transistor speed to less than 100 Hz. Here, we demonstrate that an emerging class of polymer electrolytes known as ion gels can serve as printable, high-capacitance gate insulators in organic thin-film transistors. The specific capacitance exceeds that of conventional ceramic or polymeric gate dielectrics, enabling transistor operation at low voltages with kilohertz switching frequencies.     

Stretchable graphene transistors with printed dielectrics and gate electrodes

With the emergence of human interface technology, the development of new applications based on stretchable electronics such as conformal biosensors and rollable displays are required. However, the difficulty in developing semiconducting materials with high stretchability required for such applications has restricted the range of applications of stretchable electronics. Here, we present stretchable, printable, and transparent transistors composed of monolithically patterned graphene films. This material offers excellent mechanical, electrical, and optical properties, capable of use as semiconducting channels as well as the source/drain electrodes. Such monolithic graphene transistors show hole and electron mobilities of 1188 ± 136 and 422 ± 52 cm(2)/(V s), respectively, with stable operation at stretching up to 5% even after 1000 or more cycles.     

Electrical properties of 10-nm-radius n-type gate all around twin Si nanowire field effect transistors

The electrical properties of 10-nm-radius n-type gate all around (GAA) twin Si nanowire field effect transistors (TSNWFETs) and field effect transistors (FETs) without nanowires were investigated to understand their device characteristics. The electrical characteristics of the GAA TSNWFETs and FETs with bulk boron concentrations of 1 x 10(18) and 1 x 10(16) cm(-3) were simulated by using three-dimensional technology computer-aided design simulation tools of sentaurus taking into account quantum effects. The simulation results showed that the on-current level of the TSNWFETs was larger than that of FETs, and the subthreshold swing and the drain induced barrier lowing of the TSNWFETs were smaller than those of FETs. The current density and conduction band edge profiles in the TSNWFETs clarified the dominant current paths. The simulation results showed that the on-current/off-current ratio increased with increasing bulk boron concentration, and the stand-by current level decreased.     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

Optical switching of porphyrin-coated silicon nanowire field effect transistors

We study porphyrin derivative coated silicon nanowire field effect transistors (SiNW-FETs), which display a large, stable, and reproducible conductance increase upon illumination. The efficiency and the kinetics of the optical switching are studied as a function of gate voltage, illumination wavelength, and temperature. The decay kinetics from the high- to the low-conductance state is governed by charge recombination via tunneling, with a rate depending on the state of the SiNW-FET. The comparison to porphyrin-sensitized carbon nanotube FETs allows the environment- and molecule-dependent photoconversion process to be distinguished from the charge-to-current transducing effect of the semiconducting channel.     

Electrical characterization of composition modulated In(1-x)Sb(x) nanowire field effect transistors by scanning gate microscopy

In this work high quality crystalline In(1_x)Sb(x) nanowires (NWs) are synthesized via a template-based electrochemistry method. Energy dispersive spectroscopy studies show that composition modulated In(1-x)Sb(x) (x approximately 0.5 or 0.7) nanowires can be attained by selectively controlling the deposition potential during growth. Single In(1-x)Sb(x) nanowire field effect transistors (NW-FETs) are fabricated to study the electrical properties of as-grown NWs. Using scanning gate microscopy (SGM) as a local gate the I(ds)-V(ds) characteristics of the fabricated devices are modulated as a function of the applied gate voltage. Electrical transport measurements show n-type semiconducting behavior for the In0.5Sb0.5 NW-FET, while a p-type behavior is observed for the In0.3Sb0.7 NW-FET device. The ability to grow composition modulated In(1-x)Sb(x) NWs can provide new opportunities for utilizing InSb NWs as building blocks for low-power and high speed nanoscale electronics.     

Fabrication and characterization of nano-channel field effect transistors patterned by AFM anodic oxidation

We report a top-down approach based on atomic force microscope (AFM) local anodic oxidation (LAO) for the fabrications of the nanowire and nano-ribbon field effect transistors (FETs). In order to investigate the transport characteristics of nano-channel, we fabricated simple FET structures with channel width W approximately 300 nm (nanowire) and 10 microm (nano-ribbon) on 20 nm-thick silicon-on-insulator (SOL) wafers. In order to investigate the transport behavior in the device with different channel geometries, we have performed detailed two-dimensional simulations of nanowire and reference nano-ribbon FETs with a fixed channel length L and thickness t but varying channel width W from 300 nm to 10 microm. By evaluating the charge distributions, we have shown that the increase of 'on state' conduction current in SiNW channel is a dominant factor, which consequently result in the improved on/off current ratio of the nanowire FET.     

Single ZnO nanowire-PZT optothermal field effect transistors

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.     

Stability of pentacene organic field effect transistors with a low-k polymer/high-k oxide two-layer gate dielectric

This paper reports on the processing and the characterization of pentacene organic field effect transistors (OFETs) with a two-layer gate dielectric consisting of a polymer (PMMA) on a high-k oxide (Ta₂O₅). This dielectric stack has been designed in view to combine low voltage operating devices, by the use of a high-k oxide which increases the charge in the accumulation channel and the gate capacitance, and highly stable devices which generally could be achieved with polymer dielectrics but not necessarily with strongly polar high-k oxides. Bi-layer dielectric devices were compared to those with only Ta₂O₅ or PMMA gate insulators. Bias stress at room temperature was used to assess the electrical stability. A very low operating voltage was achieved with Ta₂O₅ but these devices exhibit hysteresis and degraded characteristics upon bias stress. OFETs with PMMA revealed very stable but operate at rather a high voltage due to the low dielectric constant of PMMA. Reasonably stable devices operating at about 10 V could have been obtained with PMMA/Ta₂O₅ two-layer dielectric. The origin of observed threshold voltage shift and mobility decrease upon bias stress are discussed.     

Gate coupling and charge distribution in nanowire field effect transistors

We have modeled the field and space charge distributions in back-gate and top-gate nanowire field effect transistors by solving the three-dimensional Poisson's equation numerically. It is found that the geometry of the gate oxide, the semiconductivity of the nanowire, and the finite length of the device profoundly affect both the total amount and the spatial distribution of induced charges in the nanowire, in stark contrast to the commonly accepted picture where metallic dielectric properties and infinite length are assumed for the nanowire and the specific geometry of the gate oxide is neglected. We provide a comprehensive set of numerical correction factors to the analytical capacitance formulas, as well as to numerical calculations that neglect the semiconductivity and finite length of the nanowire, that are frequently used for quantifying carrier transport in nanowire field effect transistors.     

Field dependent transport properties in InAs nanowire field effect transistors

We present detailed studies of the field dependent transport properties of InAs nanowire field-effect transistors. Transconductance dependence on both vertical and lateral fields is discussed. Velocity-field plots are constructed from a large set of output and transfer curves that show negative differential conductance behavior and marked mobility degradation at high injection fields. Two dimensional electrothermal simulations at current densities similar to those measured in the InAs NWFET devices indicate that a significant temperature rise occurs in the channel due to enhanced phonon scattering that leads to the observed mobility degradation. Scanning transmission electron microscopy measurements on devices operated at high current densities reveal arsenic vaporization and crystal deformation in the subject nanowires.     

Degradation pattern of SnO(2) nanowire field effect transistors

The degradation pattern of SnO(2) nanowire field effect transistors (FETs) was investigated by using an individual SnO(2) nanowire that was passivated in sections by either a PMMA (polymethylmethacrylate) or an Al(2)O(3) layer. The PMMA passivated section showed the best mobility performance with a significant positive shift in the threshold voltage. The distinctive two-dimensional R(s)-μ diagram based on a serial resistor connected FET model suggested that this would be a useful tool for evaluating the efficiency for post-treatments that would improve the device performance of a single nanowire transistor.     

Fabrication and characterization of Ga-doped ZnO nanowire gas sensor for the detection of CO

We demonstrate an efficient CO sensor using Ga-doped ZnO (GZO) nanowires (NWs). Various GZO NWs are synthesized with Au catalysts on sapphire substrates by hot-walled pulse laser deposition. The deposition temperature of ZnO NWs was in the range of 800-900 °C. Scanning electron microscopy (SEM), X-ray diffraction (XRD) and photoluminescence (PL) characterizations indicate that the obtained NWs have the well-crystallized hexagonal structure with customized Ga-doping concentration of 0-5 wt.%. The NWs have the diameter of about 50 nm and the length of about 8 µm. After depositing the Ag electrodes on both sides of the NW cluster, the resistance change is checked with the exposure to CO gas in the self-designed gas chamber that can facilitate the detection of the resistance change and the control of gas flow as well as temperature. The detected resistance modulations are 1.0 kΩ and 83.2 kΩ in the cases of 3 wt.% GZO and pure ZnO NW clusters, respectively, indication that we successfully customize the sensitivity of the gas sensors by controlled doping.     

High-performance polycrystalline silicon thin-film transistors with oxide-nitride-oxide gate dielectric and multiple nanowire channels

This work presents a method to enhance the performance of polycrystalline silicon thin film transistors (poly-Si TFTs) by using an oxide-nitride-oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics compared to other TFTs. This is because a structure with more corners and a shorter radius has better gate control due to the corner effect.