无线传感器网络泛洪时间同步协议安全算法

针对无线传感器网络泛洪时间同步协议(FTSP)可能遭受到基于发送时间标攻击的问题,提出一种安全算法,在FTSP中添加异常漂移率检测器和恶意节点ID号过滤器,同时为进一步提高FTSP的同步精度,减小FTSP受到恶意攻击后对时间同步的影响,改进泛洪时间同步协议中计算时钟漂移率的公式,对其进行加权处理。仿真结果表明:该安全算法能够有效地防御基于发送时间标的恶意攻击,减小了计算开销和恶意攻击对算法的影响,鲁棒性增强,同时提高了同步精度,达到了稳定准确的同步效果。     

基于RTEthernet改进的时钟同步算法

以太网其庞大的网络系统在复杂的环境中存在网络链路延迟,节点时钟的漂移,同步能力差等问题。通过研究RTEthernet协议的起源和工作原理,考虑到影响实时以太网时间同步精密度的时钟拜占庭故障、网络传输延迟和漂移率等三个因素,建立了符合RTEthernet协议的通信模型。对FTA时钟同步算法在故障下时钟同步精密度损失率提升较少的问题进行了研究,引入了滑动窗口技术,提出了容错滑动窗口（Fault-Tolerant Sliding Window, FTSW）算法。容错滑动窗口算法能进一步提高分布式系统在进行时钟同步是对故障节点的容错能力。最后,使用CANoe仿真工具对FTSW算法进行仿真验证, FTSW算法的容错性优于FTA时钟同步算法算法,且在系统（七个节点）中存在两个拜占庭故障的情况下,同步后的精密度损失率降低了7.1%。     

面向结构健康监测的改进FTSP算法设计

针对无线传感器网络桥梁结构健康监测同步精度低的问题,采用迭代加权最小二乘法估计及补偿时钟漂移,设计了一种基于帧首定界符(SFD)硬件捕获机制的改进泛洪时间同步算法(FTSP),并与经典FTSP算法进行对比研究。根据桥梁结构,选用线性链状网络拓扑结构,在CC2530硬件平台上测得单跳网络平均同步误差为3. 148μs,3跳网络平均同步误差为9. 167μs。试验结果表明,改进FTSP算法有效地解决了发送延迟、访问延迟、接收延迟,以及异常数据对时间同步精度及稳定性影响的问题,是一种满足桥梁结构健康监测应用的高精度、高稳定性时间同步算法。     

基于可变时隙与动态同步的端口跳变技术研究

通过分析一般端口跳变模型的关键技术,在固定跳变时隙的基础上,提出跳端口可变时隙算法.该算法实现了一种依据人工预设、实时通信质量检测以及网络入侵等条件下,进行反馈防御的机制.分析一般时钟同步算法,提出动态时钟漂移同步算法,解决了可变时钟漂移在端口跳变模型中对时间同步影响的问题,比传统固定时钟漂移算法具有更广泛的适用性,通过实验表明了其在网络防御中的有效性.     

基于MSP430的无线传感器网络时间同步的研究与设计

时间同步是无线网路的一项重要支撑技术.传感器网络时间同步协议算法虽然能快速高效地进行网络节点上的时间同步,但是在同步时,需要对其进行组网,效率低下,且在同步的过程中没有考虑自身时钟的精度问题.针对以上不足,提出一种时间同步算法—最优时钟源传感器网络时间同步协议.该算法不需要构建网络的拓扑结构,能逐次选取优于自身节点时钟的时钟源进行同步.并用MSP430单片机设计的根节点和传感器节点构成的无线网络进行了分析验证.     

基于卡尔曼滤波的网络精确时钟同步研究

在网络化分布式测试与控制系统中,时钟同步是一项重要的课题研究指标.在基于IEEE 1588协议主从时钟的时钟同步中,时钟偏差和时钟漂移的精确测量是主从时钟同步的重要保证.提出了基于卡尔曼滤波的时钟同步方法,该方法不仅能对主从节点之间的时钟漂移进行估计、优化时钟模型,还能实现对时钟偏差的估计,消除传输网络中的干扰.实验结果表明,在时钟同步中引入卡尔曼滤波算法能显著提高时钟同步精度.     

无线传感器网络时间同步综述

无线传感器在网络应用时要求传感器节点保持时间同步,但传统的时间同步方法并不适用于无线传感器网络。为此,指出设计时间同步协议所面临的问题,对现有无线传感器网络时间同步算法进行总结,分析典型算法对时钟偏差和时钟漂移的处理,并给出进一步的研究方向。     

嵌入式设备的精确时钟同步技术的研究与实现

为解决工业以太网中嵌入式设备之间时钟同步能力不足的问题,提出了IEEE1588协议在嵌入式设备中的应用方案。基于STM32F207IG处理器和ucos-II操作系统软硬件平台,首先移植并修改LwIP协议使其兼容IEEE 1588协议,然后配置系统时间校准模式,将捕获的时间戳以增强型描述符的形式交于应用层进行时钟校正,采用频率漂移校正算法解决从时钟频率漂移的问题,使用秒脉冲信号测试时钟同步。实验测试表明,时钟同步精度约200 ns,满足了大部分工业以太网的需求。     

基于本地时钟自校正的无线传感器网络同步方法

通过分析TPSN同步协议和造成时钟偏差不确定性的各种因素,结合无线传感器网络低功耗的特点及其对时钟同步算法精度的要求,针对TPSN未对时钟频率漂移进行估计的问题,提出一种节点本地时钟自校正方法,并设计了平均时钟偏差指标对一个同步周期内时钟精度进行评价。对比实验结果表明本方法易于实现,在保证同步精度的同时可以延长同步周期,减少同步开销,节约了能耗。     

一种基于休眠机制的网络时间同步协议

时间同步技术是网络系统正常运行的基础。为了降低能耗,无线传感器网络(WSN)需要采用周期性休眠机制。针对目前WSN时间同步协议较少考虑网络节点的休眠问题,提出了一种适用于采用休眠机制的WSN时间同步协议。该协议包括递增序列号(ISN)机制和时钟校正机制。ISN同步机制能够在唤醒休眠节点的同时,将各网络节点同步到一致的时间点。随后,各节点利用本地时钟与参考节点时钟间的时钟漂移差值,对本地时钟进行校正。基于硬件平台的测试表明,该协议能够以较低的同步成本达到较高的同步精度;与传统时间同步协议相比,协议的执行不再受节点休眠状态影响,并且节点的唤醒过程与时间同步相结合,减少了同步消息的交换量;此外,协议中的时钟校正机制还可有效延长再同步周期。该协议还为众多基于时间同步的应用,如网络通信协议、时分多址(TDMA)调度及节点定位等,奠定了必要的基础。     

Integrating External and Internal Clock Synchronization

We address the problem of how to integrate fault-tolerant external and internal clock synchronization. In this paper we propose a new external/internal clock synchronization algorithm which provides both external and internal clock synchronization for as long as a majority of the reference time servers (servers with access to reference time) stay correct. When half or more of the reference time servers are faulty, the algorithm degrades to a fault-tolerant internal clock synchronization algorithm. We prove that at least 2 F+1 reference time servers are necessary for achieving external clock synchronization when up to F reference time servers can suffer arbitrary failures, thus the proposed algorithm provides maximum fault-tolerance. In this paper we also derive lower bounds for the best maximum external deviation achievable in standard mode and the best drift rate achievable in degraded mode. Our algorithm is optimal with respect to these two bounds: (1) the maximum external deviation is optimal in standard mode, and (2) the drift rate of the clocks is optimal in standard and degraded mode.     

基于最优时钟偏差的无线传感器网络同步算法

针对无线传感器网络固有的时钟偏移和时钟漂移问题,研究了不同的时间同步方法对同步精度的影响。以簇形网络结构时钟同步原理为依据提出最优时钟偏差算法,应用卡尔曼滤波方法,以最优化递归方式对成员节点的时钟偏差进行最小调整。与一般簇形同步算法进行比较发现,该算法不仅可以提高同步精度,还可以减少节点能耗。仿真结果也表明,该算法能准确地描述同步精度问题,是一种有效的时钟同步算法。     

Interval-based Clock Synchronization

In this paper, we develop and analyze a simple interval-based algorithm suitable for fault-tolerant external clock synchronization. Unlike usual internal synchronization approaches, our convergence function-based algorithm provides approximately synchronized clocks maintaining both precision and accuracy w.r.t. external time. This is accomplished by means of a time representation relying on intervals that capture external time, providing accuracy information encoded in interval lengths. The algorithm, which is generic w.r.t. the convergence function and relies on either instantaneous correction or continuous amortization for clock adjustment, is analyzed by utilizing a novel, interval-based framework for establishing worst-case precision and accuracy bounds subject to a fairly detailed system model. Apart from individual clock rate and transmission delay bounds, our system model incorporates non-standard features like clock granularity and broadcast latencies as well. Relying on a suitable notion of internal global time, our analysis unifies treatment of precision and accuracy, ending up in striking conceptual beauty and expressive power.     

基于卡尔曼滤波估计的一致性时钟同步算法

针对无线传感器网络（WSN）的众多应用都需要依赖时钟同步的节点协同完成,而由于节点的晶体震荡器受自身以及外界环境的影响,使得节点时钟偏斜和时钟偏移两个参数发生变化导致时钟不同步问题,提出了基于分布式卡尔曼滤波估计的一致性补偿时钟同步算法DKFCC。该算法首先利用双向信息交换机制以及分布式卡尔曼滤波实现时钟偏斜和偏移两个参数的最优估计,然后基于时钟参数的最优估计值采用一致性补偿方法实现节点的时钟同步。实验结果表明：在100个节点随机部署的WSN中,采用虚拟全局一致性方式的DKFCC同步算法比异步一致性同步（AC）算法的同步均方根误差（SRAMSE）值降低了约95%,具有较高的同步精度;同时,所提出算法从时钟参数层面实现同步,无需频繁地进行时钟同步操作,相比AC算法更节能。     

Multistep interactive convergence: an efficient approach to thefault-tolerant clock synchronization of large multicomputers

We present a new approach for fault-tolerant internal clock synchronization in multicomputer systems employing not completely connected networks (NCCNs). The approach is referred to as multistep interactive convergence and is locally implemented in each multicomputer node by a time server process (TSP). We describe a specific algorithm that uses multistep interactive convergence and bases its operation on a logical mapping of the system's TSPs into an m-dimensional array. A TSP executes m steps per round of synchronization, with each step including a call to an interactive convergence procedure. For any TSP, clock readings in step i are gathered only from TSPs with which it shares a row along dimension i of the array. Hence, a TSP reads clocks only from a small subset of the TSPs in the system, which reduces the number of messages by orders of magnitude over a conventional interactive convergence algorithm in which reliable all-to-all broadcast of clock values is done. The algorithm can be used in systems of arbitrary topology and provides the added benefit of increased locality of communication in regular NCCNs such as hypercubes and tori. These advantages can be combined with a variety of message staggering mechanisms to maintain network contention at a minimum. We present expressions for the maximum clock skew, maximum clock drift, maximum clock discontinuity, and number of messages produced by the algorithm, and show that it tolerates arbitrary faults. A comparison with other algorithms that elucidates the advantages of multistep interactive convergence is also provided     

Combination of clock-state and clock-rate correction in fault-tolerant distributed systems

This paper proposes the integration of internal and external clock synchronization by a combination of a fault-tolerant distributed algorithm for clock state correction with a central algorithm for clock rate correction. By means of hardware and simulation experiments it is shown that this combination improves the precision of the global time base in a distributed single cluster system while reducing the need for high-quality oscillators. Simulation results have shown that the rate-correction algorithm contributes not only in the internal clock synchronization of a single cluster system, but it can be used for external clock synchronization of a multi-cluster system with a reference clock. Therefore, deployment of the rate-correction algorithm integrates internal and external clock synchronization in one mechanism. Experimental results show that a failure in the clock rate correction will not hinder the distributed fault-tolerant clock state synchronization algorithm, since the state correction operates independently from the rate correction. The paper introduces new algorithms and presents experimental results on the achieved improvements in the precision measured in a time-triggered system. Results of simulation experiments of the new algorithms in single-cluster and multi-cluster configurations are also presented. Hermann Kopetz (Fellow, IEEE) received the Ph.D. degree in physics ísub auspiciis praesidentis from the University of Vienna, Vienna, Austria, in 1968. He was Manager of the Computer Process Control Department at Voest Alpine, Linz, Austria, and Professor of Computer Process Control, Technical University of Berlin, Berlin, Germany. He is currently Professor of Real-Time Systems, Vienna University of Technology, Vienna, Austria, and a Visiting Professor at the University of California, Irvine, and the University of California, Santa Barbara. In 1993, he was offered a position as Director of the Max Planck Institute, Saarbrcken, Germany. Prof. Kopetz is the key architect of the Time-Triggered Architecture. Astrit Ademaj (IEEE member) received the Dipl-Ing. degree (1995) at the University of Prishtina, Kosova, and a doctoral degree (2003) in computer science from the Technical University of Vienna. He is currently working as Assistant Professor at the Technical University of Vienna and as a Visiting Lecturer at the University of Prishtina. His research interests are design and validation of communication systems for safety-critical and real-time applications. He is a member of the IEEE Computer Society. Alexander Hanzlik received a diploma (1995) and a doctoral degree (2004) in computer science from the Technical University of Vienna. From 1995 to 1998, he was concerned with voice communication system design for air traffic control for the Service de Navigation Aérienne (STNA). Since 1998, his focus is on embedded systems in the fields of telecommunication, automation and process control. Since 2001, Dr. Hanzlik is a member of the Real-Time Systems Group and works as a research assistant at the Technical University of Vienna. His main research activities deal with fault-tolerant clock synchronization in distributed systems and simulation. Currently, he is working on SIDERA, a simulation model for time-triggered, dependable real-time architectures.     

无线传感器网络中带延时的一致性时间同步

针对无线传感器网络(WSNs)中节点间通信存在传输延迟,影响同步精度的情况,将加权平均应用于相对时钟斜率的计算,提出了一种带延时的一致性时间同步算法.该算法中每个传感器节点通过与邻居节点通信交换时钟信息,根据一致性理论更新时钟参数,从而到达时间同步的目的.研究了在假定传输延时服从正态分布的情况下对一致性时间同步算法的影响,提出的算法降低了延时对同步精度的影响,Matlab仿真验证了该算法的有效性.