FLOTOXEEPROM擦写过程中隧道氧化层陷阱俘获电荷的研究

本文首先从理论上分析FLOTOX EEPROM隧道氧化层中陷阱俘获电荷对注入电场和存储管阈值电压的影响,然后给出了在不同擦写条件下FLOTOX EEPROM存储管的阈值电压与擦写周期关系的实验结果,接着分析了在反复擦写过程中陷阱俘获电荷的产生现象.对于低的擦写电压,擦除阈值减少,在隧道氧化层中产生了负的陷阱俘获电荷;对于高的擦写电压,擦除阈值增加,产生了正陷阱俘获电荷.这一结果与SiO₂中电荷的俘获——解俘获动态模型相吻合.     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

二氧化硅薄膜驻极体的电荷特性

对二氧化硅薄膜驻极体中几种主要电荷的基本特性－固定氧化物电荷的特性特性、氧化物陷阱电荷的特性及硅－二氧二硅界面陷阱电荷的特性进行了分析。     

SONOS存储单元数据保持特性退化研究

探讨了基于Fowler-Nordheim(F-N)隧穿进行编程、擦除的硅-氧化物-氮化物-氧化物-硅(SONOS)存储单元在擦写循环后的数据保持特性。分别通过分析和实验研究了擦写过程中操作电压大小对于VTH(编程)态、VTL(擦除)态存储单元数据保持性能退化的影响。对于VTH态单元,其数据保持性能退化程度受操作电压大小的影响不明显,电荷流失速度主要受温度影响；而VTL态单元数据保持性能退化程度受操作电压大小的影响较大,电荷流失速度与温度的关系不明显。通过对比不同操作条件下进行擦写循环后的数据保持性能退化程度,总结了有利于减小SONOS存储器数据保持性能退化的操作条件。     

CTM俘获层材料选取的模拟研究

电荷陷阱存储器(CTM)由于其分离式电荷存储原理,可以使存储器件尺寸持续小尺寸化,理论上解决了传统浮栅存储器小尺寸化瓶颈的限制。基于第一性原理,从理论上对CTM材料及相关结构进行了模拟计算,采用Material Studio软件包,对多种电荷俘获材料进行改性,引入陷阱,并对其能带、状态密度、缺陷态密度等方面展开模拟研究。为CTM实验提供了非常有效的理论依据与方法,从该角度出发研究存储器是一个全新的视角,提出可以通过陷阱态密度曲线的部分积分来确定CTM的存储窗口等衡量指标。     

EEPROM单元的电荷保持特性

利用理论推导和实验方法对电可擦除可编程只读存储器EEPROM单元在给定电压下的电荷保持特性进行了分析和研究,得出了EEPROM单元电荷保持能力的理论公式,得到了单元保持状态下的电特性曲线,发现在双对数坐标下,阈值电压的退化率与时间成线性关系.在假定电荷流失机制为Fowler-Nordheim隧穿效应的情况下,推出了EEPROM单元在给定外加电压下的电荷保持时间,并通过实验得出了简化的EEPROM单元寿命公式.     

陷阱电荷对GMLM工作电压的影响

光栅平动式光调制器(GMLM)依靠可动光栅在静电力作用下向下反射镜移动,从而改变光程差,实现光调制.结构中siO2绝缘层在外加电场作用下产生陷阱电荷,对器件的驱动特性产生影响.作者依据高斯定理,建立GMLM存在陷阱电荷情况下的电力学模型,分析了外加电场作用下,GMLM极板电荷的分布,以及外加电压与可动光栅位移的关系;比较了两种情况下(考虑与不考虑绝缘层陷阱电荷影响)工作电压变化情况.设计了实验方案,进行了实验研究.结果表明:由于陷阱电荷产生陷阱电压,使得产生相同位移需要的工作电压增加;充电时间越长,陷阱电荷产生的陷阱电压越大;实验结果与理论分析吻合.     

陷阱电荷对GMLM工作电压的影响

光栅平动式光调制器(GMLM)依靠可动光栅在静电力作用下向下反射镜移动,从而改变光程差,实现光调制.结构中siO2绝缘层在外加电场作用下产生陷阱电荷,对器件的驱动特性产生影响.作者依据高斯定理,建立GMLM存在陷阱电荷情况下的电力学模型,分析了外加电场作用下,GMLM极板电荷的分布,以及外加电压与可动光栅位移的关系;比较了两种情况下(考虑与不考虑绝缘层陷阱电荷影响)工作电压变化情况.设计了实验方案,进行了实验研究.结果表明:由于陷阱电荷产生陷阱电压,使得产生相同位移需要的工作电压增加;充电时间越长,陷阱电荷产生的陷阱电压越大;实验结果与理论分析吻合.     

VDMOS异常峰值电流产生原因研究

研究了VDMOS器件存在异常峰值电流的原因,提出了解释此现象的理论。异常峰值电流的大小由VDMOS元胞在P+body区之间neck区的界面状态决定。一般MOSFET不具有此特殊结构,因而不具有此异常峰值电流现象。为了验证上述理论,采用TCAD(ISE),模拟了氧化物陷阱电荷和界面态电荷对异常峰值电流的影响程度。研究结果表明,氧化物陷阱电荷和界面态电荷显著影响neck区域的复合电流,是产生异常峰值电流最主要的原因。     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

Effect of trapped charge accumulation on the retention of charge trapping memory

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation.The recombination process between trapped charges is an important issue on the retention of charge trapping memory.Our results show that accumulated trapped holes during P/E cycling can have an influence on retention,and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.     

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET.A 0.12μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method.The trapped charge distribution with a narrow peak can be precisely characterized with this method,which shows good consistency with the measured threshold voltage.     

Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells

A new characterization technique and an improved model for charge injection and transport through ONO gate stacks are used to investigate the program/retention sequence of silicon nitride-based (SONOS/TANOS) nonvolatile memories. The model accounts for drift–diffusion transport in the conduction band of silicon nitride (SiN). A priori assumptions on the spatial distribution of the charge at the beginning of the program/retention operations are not needed. We show that the carrier transport in the SiN layer impacts the spatial distribution of the trapped charge and, consequently, several aspects of program and retention transients. A few model improvements allow us to reconcile the apparent discrepancy between the values of silicon nitride trap energies extracted from program and retention experiments, thus reducing the number of model parameters.      

Comparative Study of Quick Electron Detrapping and Random Telegraph Signal and Their Dependences on Random Discrete Dopant in Sub-40-nm NAND Flash Memory

In sub-40-nm Flash memory, random discrete dopant (RDD) effect modulates post program/erase (P/E) cycling $V_{t}$ instabilities through quick electron detrapping (QED) as well as random telegraph signal (RTS). In this letter, for the first time, we discuss the QED phenomenon and its physical origin by comparison with RTS phenomenon. P/E cycling stress not only aggravates the RTS but also generates the new phenomenon of QED which results from transiently trapped charges at near-interface defects during program. By applying a new test algorithm, we could successfully extract the QED component from RTS, both of which are modulated by RDD effect and worsen tail bits in multilevel-cell Flash memory.      

Influence of metal gate and capping film stress on TANOS cell performance

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.     

BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO₂-Si₃N₄-SiO₂ stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.     

Cycling degradation in TANOS stack

The aim of this work is to investigate the physical mechanisms behind TANOS (TaN/Alumina/Nitride/Oxide/Silicon) cycling degradation. A comparison of the degradation induced in the TANOS stack by unipolar or bipolar stress has allowed the separation the different degradation contributions. A comparison with standard floating gate (FG) stack has also been carried out to confirm these degradation mechanisms. Finally, different stack configurations are reported, showing the key factors affecting the degradation and giving trends for improving cycling degradation.     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。