Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives

This paper presents a comprehensive methodology to model the assembly process of flip chip on flex interconnections with non-conductive adhesives (NCAs). The methodology combines experimental techniques for material characterization, finite element modeling, and model validation. A non-conductive adhesive has been characterized using several techniques. A unique experimental technique has been developed to measure the cure shrinkage. A 2D axisymmetric finite element model is used for analysis of flip chip on flex package with the non-conductive adhesive (NCA), which takes into account assembly force, cure shrinkage, adhesive modulus buildup, removal of assembly force, and cooling down to room temperature. The relationship between the bump contact resistance and the bump pressure has been established through the development of a dedicated experimental setup, which uses a micro-force tester combined with a digital multimeter and a nano-voltmeter. The process modeling has been validated by comparing the predicted bump contact resistance value and the measured bump contact resistance value after assembly process. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters, and good reliability performances.     

Sn58Bi Solder Interconnection for Low‐Temperature Flex‐on‐Flex Bonding

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low‐temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low‐temperature lead‐free soldering and bonding processes as a possible alternative for flex‐on‐flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder‐on‐pad process with Solder Bump Maker based on Sn58Bi for low‐temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of 150 °C using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an 85 °C and 85% reliability test, and an SEM cross‐sectional analysis.     

The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications

The work presented in this paper focuses on the effect of reflow process on the contact resistance and reliability of anisotropic conductive film (ACF) interconnection. The contact resistance of ACF interconnection increases after reflow process due to the decrease in contact area of the conducting particles between the mating I/O pads. However, the relationship between the contact resistance and bonding parameters of the ACF interconnection with reflow treatment follows the similar trend to that of the as-bonded (i.e. without reflow) ACF interconnection. The contact resistance increases as the peak temperature of reflow profile increases. Nearly 40% of the joints were found to be open after reflow with 260 °C peak temperature. During the reflow process, the entrapped (between the chip and substrate) adhesive matrix tries to expand much more than the tiny conductive particles because of the higher coefficient of thermal expansion, the induced thermal stress will try to lift the bump from the pad and decrease the contact area of the conductive path and eventually, leading to a complete loss of electrical contact. In addition, the environmental effect on contact resistance such as high temperature/humidity aging test was also investigated. Compared with the ACF interconnections with Ni/Au bump, higher thermal stress in the Z-direction is accumulated in the ACF interconnections with Au bump during the reflow process owing to the higher bump height, thus greater loss of contact area between the particles and I/O pads leads to an increase of contact resistance and poorer reliability after reflow.     

Characterization and modeling of static and cyclic relaxation in nonconductive adhesives

Adhesive interconnections are considered to be attractive alternatives to lead or lead-free solder interconnects because of their lower processing temperatures and extendability to fine pitch applications. However, reliability issues, such as moisture-induced delamination and viscoelastic relaxation of the adhesive in both steady-state and cyclic loading, continue to pose a challenge to widespread implementation. To date, the static and cyclic relaxation characteristics of nonconductive adhesives (NCAs) are yet to be understood. This paper attempts to provide insights into this static and cyclic relaxation behavior through experimental characterization and modeling. The viscoelastic property of a typical NCA material was characterized, and a simulation program with integrated circuit emphasis (SPICE) modeling program was used to model the cyclic relaxation behavior. The modeling results were successfully validated with a series of experiments. This showed that cyclic relaxation of the adhesive can be successfully modeled using linear-viscoelastic property. The phenomenon of slower relaxation of the adhesive under cyclic loading than that in static loading suggests that accelerated reliability testing used in solder-joint fatigue durability investigations may not be directly applicable to the adhesive interconnections. A rework methodology applicable to adhesive interconnects using cyclic loading has also been proposed.     

Effect of Conductive Particle Properties on the Reliability of Anisotropic Conductive Film for Chip-on-Glass Applications

This paper describes how the material properties of conductive particles in anisotropic conductive films (ACFs) affect the electrical conductivity and the reliability of ACF interconnections for chip-on-glass (COG) applications. For the conductive particles, Au/Ni-coated polymer particles with a 5-diameter were used. Two different types of conductive particles were characterized with respect to their mechanical and electrical properties, such as ball hardness, recovery behavior, and electrical resistance. In addition, two ACFs were fabricated in the form of a double-layered structure, in which the thickness of the ACF and a nonconductive film (NCF) layer were optimized to have as many conductive particles as possible on the bump after COG bonding. The electrical contact resistance of an ACF interconnection in a COG structure depends mainly on the electrical properties of conductive particles in the ACF. The electrical reliability of an ACF interconnection in a COG structure also depends more on the electrical properties than the mechanical properties of conductive particles under a high-temperature and humid condition. Conductive particles with a lower electrical resistance, higher mechanical hardness, and lower recovery rate show better reliability than conductive particles with a higher electrical resistance, lower mechanical hardness, and higher recovery rate. Cross-sectional scanning electron microscopic (SEM) pictures of a COG interconnection show the deformation of two different conductive particles after the reliability tests. The ACF interconnections in the edge or corner of a driver IC show less reliable joints due to high absorption of moisture.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Polysilicon thin-film transistors on polymer substrates

Different approaches to fabricate low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) on polymer substrates are reviewed and the two main routes are discussed: (1) standard fabrication of LTPS TFTs on glass substrates followed by a transfer process of the devices on the polymeric substrate; (2) direct fabrication of the devices on the polymeric substrate. Among the different techniques we have described in more detail the process we have recently developed for the fabrication of LTPS TFTs directly on ultra-thin polyimide (PI) substrate. LTPS TFT technology is particularly suited for high performance flexible electronics applications, due to the excellent device characteristics, good electrical stability and CMOS technology. Flexible display application remains the most attractive application for LTPS technology, especially for AMOLED displays, where device stability and the possibility to integrate the driving circuits make LTPS technology superior to all the other competitive TFT technologies. Among the other applications, particularly promising is also the application to flexible smart sensors, where integration of a front-end electronics is essential. Some examples of flexible gas sensors and pressure sensors, integrated with simple readout electronics based on LTPS TFTs and fabricated on ultra-thin PI substrate, are presented.     

Integrated packaging of over 100 GHz bandwidthuni-traveling-carrier photodiodes

Hybrid packaging techniques, in which the device substrate is different from the package substrate, and wire bonding or solder interconnections are used, are inadequate for ultrahigh-speed (>100 GHz) wideband applications. By employing wafer-bonding techniques, an integrated packaging (IP) technology was developed, in which devices are fabricated directly on the package substrate, and the interconnections are made as a part of the device fabrication process. This IP process was used to fabricate uni-traveling-carrier photodiodes (UTC-PD's) integrated with millimeter-wave coplanar waveguides (CPW) on package compatible sapphire with high yield. The performance of wafer-bonded UTC-PD's with 3-dB bandwidth of 102 GHz was similar to that of conventional devices, and the CPW's exhibited low dispersion     

Reliability model for Al wire bonds subjected to heel crack failures

In power electronic packages wire bonding is used for the electrical contact of the chips and for interconnections on the module substrate. Limiting factors for the reliability are solder fatigue and wire bond failures. In this work we investigate the material fatigue of aluminum bonding wires stressed by cyclic lateral bonding area displacement. Bond wire heel crack failures observed by experiments are found to be strongly dependent on the loop geometry. Based on a finite element model that accounts for elastic-plastic material properties, a life-time model for the Al wire (Coffin-Manson representation) is derived from the experiments.     

Flip Chip Assembly of Thinned Silicon Die on Flex Substrates

Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.     

Electrical Characterization of NCP- and NCF-Bonded Fine-Pitch Flip-Chip-on-Flexible Packages

Electronic portable devices are aimed towards higher response speed with a better viewing resolution display. Nonconductive paste (NCP) and nonconductive film (NCF) are the adhesive materials used in fine-pitch display applications. This study compares two commercially available adhesives for fine-pitch chip-on-flex (COF) applications. The electrical performance of the NCP-bonded COF was better compared to the NCF. The rheological properties of these materials in the initial stages and the mechanical properties of the adhesives after bonding are claimed to be the main factors. The semisolid form of the NCF which melts and flows slowly from the interconnection joints finally reduced the effective contact area in the joint as compared to the NCP. A low-pressure bonding caused entrapment of adhesive in the joints, induced stress accumulation in the Z-direction during high thermal loading, and a high coefficient of thermal expansion (CTE) mismatch in between bumps, adhesive, and electrode traces on the flexible substrate were the key factors for the degradation of electrical conductivity. A high load of 100 N and above was recommended since the effective contact area built into the interconnection was good and reliable after 400 cycles of a thermal shock test of -55degC-125degC. The NCP with a higher elastic modulus which ensures higher stiffness and stability towards elongation gave a better reliability in this environmental test. Cross sectioning and SEM analysis provide evidence of the effective contact area of the joint before and after the thermal cycle environmental test     

Novel Nonconductive Adhesives/Films With Carbon Nanotubes for High-Performance Interconnects

Novel nonconductive adhesives/films (NCAs/NCFs) with carbon nanotubes (CNTs) for high-performance interconnects were developed. A small amount of CNTs inside NCAs/NCFs could increase the thermal conductivities and at the same time decrease the coefficient of thermal expansion (CTE) for high thermomechanical reliability of the NCAs/NCFs' interconnect joints. Thermal mechanical analyzer measurements showed that the CTE value of the 0.03 wt% CNT filled NCAs/NCFs was significantly decreased. Current–voltage characterizations showed that the current carrying capabilities of the CNT (0.03 wt%) filled NCAs/NCFs were increased by 14% compared to the unfilled NCAs/NCFs due to the more efficient thermal dissipation and higher electrical conductivity by CNTs.      

Electrical Characterization of NCP- and NCF-Bonded Fine-Pitch Flip-Chip-on-Flexible Packages

Electronic portable devices are aimed towards higher response speed with a better viewing resolution display. Nonconductive paste (NCP) and nonconductive film (NCF) are the adhesive materials used in fine-pitch display applications. This study compares two commercially available adhesives for fine-pitch chip-on-flex (COF) applications. The electrical performance of the NCP-bonded COF was better compared to the NCF. The rheological properties of these materials in the initial stages and the mechanical properties of the adhesives after bonding are claimed to be the main factors. The semisolid form of the NCF which melts and flows slowly from the interconnection joints finally reduced the effective contact area in the joint as compared to the NCP. A low-pressure bonding caused entrapment of adhesive in the joints, induced stress accumulation in the Z-direction during high thermal loading, and a high coefficient of thermal expansion mismatch in between bumps, adhesive, and electrode traces on the flexible substrate were the key factors for the degradation of electrical conductivity. A high load of 100 N and above was recommended since the effective contact area built into the interconnection was good and reliable after 400 cycles of a thermal shock test of -55degC-125degC. The NCP with a higher elastic modulus which ensures higher stiffness and stability towards elongation gave a better reliability in this environmental test. Cross sectioning and scanning electron microscopy analysis provide evidence of the effective contact area of the joint before and after the thermal cycle environmental test     

Effect of Contact Mode on the Electrical Transport and Field‐Emission Performance of Individual Boron Nanowires

Vapor–liquid–solid processing of boron nanowires (BNWs) can be carried out either using a bottom‐up or top‐down growth mode, which results in different contact modes between the nanowire and the substrate. The contact mode may strongly affect the electrical transport and field‐emission performance of the individual boron nanowires grown on a Si substrate. The electrical transport and field‐emission characteristics of individual boron nanowires of different contact modes are investigated in situ using a scanning electron microscope. The contact barriers are very distinct for the different contact modes. Moreover, the transition from a “contact‐limited” to a “bulk‐limited” field‐emission (FE) process is demonstrated in nanoemitters for the first time, and the proposed improved metal–insulator–vacuum (MIV) model may better illustrate the nonlinear behavior of the Fowler‐Nordheim (FN) plots in these nanoscale systems. Individual BNWs with different contact modes have a discrepancy in their emission stability and vacuum breakdown characteristics though they have similar aspect ratios, which suggests that their electrical transport and field‐emission performance are closely related to their contact mode. Boron nanowires grown in the base‐up mode have better field‐emission performances and are more beneficial than those grown in the top‐down mode for various device applications.     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Materials and processes for implementing high-temperature liquid interconnects

This paper describes the results of a study investigating liquid solder joints at elevated temperatures (up to 200/spl deg/C). The reactions of eutectic 52In/48Sn solder, which melts at 118/spl deg/C, with various metal barrier layers is presented. The main emphasis of the research was to find a combination of solder and substrate metallization which has good adhesion strength but also remains stable during temperature cycling and high-temperature storage when the solder is molten. Intermetallic growth rates and solder-substrate adhesion strength have been measured for a range of potential barrier layers including Ni, Cr, Pt, Ti, V, Nb, Ta, and W. Of these, only Nb was found to have acceptable properties for a high-temperature barrier layer to In/Sn solder. Other aspects of liquid solder interconnections that have been studied include stability of the molten solder-underfill interface under electrical bias and retention of electrical contact during vibration and phase change. Plastic ball grid array (PBGA) devices have been assembled with Nb barrier layers and liquid solder joints and their reliability during temperature cycling (-20/spl deg/C to +180/spl deg/C) has been compared to PBGA joints with Sn95.5/Ag4/Cu0.5 solder balls.     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

Low‐Resistant Electrical and Robust Mechanical Contacts of Self‐Attachable Flexible Transparent Electrodes with Patternable Circuits

Flexible, transparent, conductive electrodes are key elements of emerging flexible electronic and energy devices. Such electrodes should form an intimate physical contact with various active components of flexible devices to ensure stable, low‐resistant electrical contacts. However, contact formation techniques are based largely on conventional soldering, conductive pastes, mechanical clamping, and thin film deposition. These generally result in damaged, contaminated, bulky, and uncontrollable contact interfaces. A self‐attachable, flexible, transparent, and conductive electrode that is based on a distinctive design of regular grid patterns into which bioinspired adhesive architectures and percolating Ag nanowires are integrated is proposed. Based on this integrated design, the proposed electrode forms reliable, low‐resistant electrical contacts; strong mechanical adhesive contacts; and ultra‐clean, damage‐free contact interfaces with active device components by attaching onto the components without using additional conductive pastes, mechanical pressing, or vacuum deposition processes. The contact interfaces of the electrode and device components remain stable even when the electrode is extremely bent. Moreover, specific electronic circuits can be generated on the electrode surface by a selective deposition of Ag nanowires. This enables simple interconnections of diverse electronic components on its surface.     

Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET

The stability of metal layers on semiconductors is a key issue for the device electrical performances. Therefore, the reliability of SiC/Ti/Pt/Au system was investigated using storage steady-stress testing, AES (Auger Electron Spectrometry), and SIMS (Secondary Ions Mass Spectrometry) analysis. The study was conducted on different patterns for gate and interconnection structure to underline the different reliability problems. Auger and SIMS analysis showed important modifications in the three-metal structure without reactions with the SiC substrate. The resistance degradation was assigned to interdiffusion phenomena. It was analyzed with a diffusion-controlled model. Activation energies and mean time to failure (MTF) were calculated for a failure criterion defined as a 10% increase of the resistance. Finally, the different rules of the metallization degradation in MESFET behaviours for interconnections and gate were discussed.