Challenges of 22 nm and beyond CMOS technology

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new devi...     

Microlithography: trends, challenges, solutions, and their impact on design

With lithography parameters approaching their limits, continuous improvement requires increasing dialogues and compromises between the technology and design communities. Only with such communication can semiconductor manufacturers reach the 30 nm physical-gate-length era with optical lithography. Optical lithography is an enabling technology for transistor miniaturization. With the wavelength and numerical aperture of exposure systems approaching their limits, the semiconductor industry needs continuous reduction of the k/sub 1/ factor. Challenges include image quality improvement, proximity effect correction, and cost control. An indispensable ingredient for future success is improvement in the design-manufacture interface.     

Fully depleted SOI (FDSOI) technology

Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances of legacy technology when retrofitting to old technology nodes. In this paper, we provide an overview of FDSOI technology, including the benefits and challenges in FDSOI design, manufacturing, and ecosystem. We articulate that FDSOI is potential cornerstone for China to catch up and leapfrog in semiconductor technology.     

Fabrication of Fresnel zone plates with high aspect ratio by soft X-ray lithography

High focusing efficiency Fresnel zone plates for hard X-ray imaging is fabricated by electron beam lithography, soft X-ray lithography, and gold electroplating techniques. Using the electron beam lithography, Fresnel zone plates which has an outermost zone width of 100 nm and thickness of 250 nm has been fabricated. Fresnel zone plates with outermost zone width of 150 nm and thickness of 660 nm has been fabricated by using soft X-ray lithography.     

Fabrication of nanoscale tungsten tip arrays for scanning probemicroscopy-based devices

A new fabrication process for nanoscale tungsten tip arrays was developed for scanning probe microscopy-based devices. It is suitable to make a huge array on a device chip and is potentially compatible with CMOS technology. In this study, tungsten was selected as a tip material because of its hardness and conductivity. The newly developed fabrication process mainly consists of several important techniques: a combination of optical lithography and electron beam (EB) lithography to reduce the total exposure time with high resolution and chromium/tungsten/chromium (Cr/W/Cr) sandwich deposition and etching in which the first chromium layer is used as a mask and a second one is used as an etch stop. A periodic array of dots in an EB resist with a spot diameter of less than 50 nm was obtained by a combination of optical lithography and EB lithography with a positive resist (polymethylmethacrylate) in which all processing conditions were optimized carefully. A thin and uniform chromium film, deposited by ion-beam sputtering, allowed the use of thin polymethylmethacrylate (PMMA) film which led to the high resolution. The conditions of dc magnetron sputtering were also optimized in order to deposit a densely packed and low-resistivity film. The resulting tungsten tip arrays had a cylindrical shape with diameters of less than 60 nm and heights of 300 nm     

Fabrication of X-ray imaging zone plates by e-beam and X-ray lithography

X-ray imaging and microscopy techniques have been developed in worldwide due to their capabilities of large penetration power and high spatial resolution. Fresnel zone plates is considered to be one of the most convenient optic devices for X-ray imaging and microscopy system. The zone plates with aspect ratio of 7 and 13 have been fabricated by e-beam lithography combined with X-ray lithography in this paper. Firstly, the X-ray lithography mask of zone plates with outermost zone width of 100 nm was fabricated by e-beam lithography and gold electroplating techniques. Secondly, the zone plates with gold profile thickness of 700 and 1,300 nm were replicated by X-ray lithography and gold electroplating techniques. X-ray imaging and microscopy techniques were introduced to characterize the high-aspect-ratio zone plates’ inner structures. At the X-ray energy of 7.5 keV, the first-order focusing efficiency of zone plates with gold profile thickness of 700 nm is about 8.63%.     

Regularized level-set-based inverse lithography algorithm for IC mask synthesis

Inverse lithography technology(ILT)is one of the promising resolution enhancement techniques,as the advanced IC technology nodes still use the 193 nm light source.In ILT,optical proximity correction(OPC)is treated as an inverse imaging problem to find the optimal solution using a set of mathematical approaches.Among all the algorithms for ILT,the level-set-based ILT(LSB-ILT)is a feasible choice with good production in practice.However,the manufacturability of the optimized mask is one of the critical issues in ILT;that is,the topology of its result is usually too complicated to manufacture.We put forward a new algorithm with high pattern fidelity called regularized LSB-ILT implemented in partially coherent illumination(PCI),which has the advantage of reducing mask complexity by suppressing the isolated irregular holes and protrusions in the edges generated in the optimization process.A new regularization term named the Laplacian term is also proposed in the regularized LSB-ILT optimization process to further reduce mask complexity in contrast with the total variation(TV)term.Experimental results show that the new algorithm with the Laplacian term can reduce the complexity of mask by over 40%compared with the ordinary LSB-ILT.     

Dual layer photoresist complimentary lithography applied on sapphire substrate for producing submicron patterns

In this study, the combined technologies of dual-layer photoresist complimentary lithography (DPCL), inductively coupled plasma-reactive ion etching and laser direct-write lithography are applied to produce the submicron patterns on sapphire substrates. The inorganic photoresist has almost no resistance for chlorine containing plasma and aqueous acid etching solution. However, the organic photoresist has high resistance for chlorine containing plasma and aqueous acid etching solution. Moreover, the inorganic photoresist is less etched by oxygen plasma etching process. The organic and inorganic photoresist deposit sequentially into a composite photoresist on a substrate. The DPCL takes advantages of the complementary chemical properties of organic and inorganic photoresist. We fabricated two structures with platform and non-platform structure. The non-platform structure featured structural openings, the top and bottom diameters and the depth are approximately 780, 500 and 233 nm, respectively. The platform structure featured structural openings, the top and bottom diameters and the depth are approximately 487, 288 and 203 nm, respectively. The precision submicron or nanoscale patterns of large etched area and patterns with high aspect ratio can be quickly produced by this technique. This technology features a low cost but high yield production technology. It has the potential applications in fabrication of micro-/nanostructures and devices for the optoelectronic industry, semiconductor industry and energy industry.     

Enhancement of the light output of GaN-based light-emitting diodes using surface-textured indium-tin-oxide transparent ohmic contacts

InGaN/GaN multi-quantum well (MQW) light-emitting diodes (LEDs) with indium tin oxide (ITO) as widow layers were fabricated. The ITO surface was textured utilizing the natural lithography combined with the inductively coupled plasma (ICP) etching technology by use of polystyrene spheres as the etching mask. The morphologies of the textured ITO surface were characterized by a scanning electron microscope (SEM) and an atomic force microscope (AFM). The electrical and optical properties of surface-textured ITO/GaN LEDs were measured and analyzed. The influence and dependence of ICP etching time on the light output of the fabricated LEDs was investigated. Experimental results indicated that ITO/GaN LEDs with nano-islands with a depth of about 120 nm and a diameter about 320 nm on the surfaces exhibited a 60% or more enhancement in the output power. The typical 20 mA driven forward voltage is only 0.2 V higher than that of conventional planar ITO/GaN LED. The fabricated surface-textured GaN LED chips from the whole 2″ wafer presented a quite good conformance in electrical and optical characteristics, and the proposed method demonstrated a good reliability. The results indicate that the surface-textured ITO method utilizing the natural lithography combined with the inductively coupled plasma (ICP) etching technology has high potential in future large-area high-power GaN LED applications.     

Modeling and optimization of thermal-flow lithography process using a neural-genetic approach

The lithography process is the most critical step in fabricating nanostructure for integrated circuit manufacturing. The most important variable in lithography process is the line width or critical dimension (CD), which perhaps is one of the most direct impact variables on the device performance and speed. This study presents a framework combining Taguchi orthogonal experiments, artificial neural network (ANN) modeling technique and genetic algorithm for sub-100 nm contact holes fabrication in lithography process. The Taguchi method utilizes S/N ratio and ANOVA to analyze the significant process parameters related to the CD, whereas the ANN establishes the relationship between controllable parameters and quality responses. The proposed Neural-Genetic approach not only can find optimal or close-to-optimal solutions but also can obtain both better and more robust results than the ANN algorithm. The confirmation results clearly demonstrated both the smaller-the-better CD and nominal-is-best CD (target 50 nm) that the proposed procedure was effective and practicable from a production perspective.     

Nanotechnology advances and applications in information storage

A brief review of some applications of nanotechnology to information storage is given with the focus on self-assembled nanoporous alumina templates for patterned media.Ordered nanoporous alumina templates were fabricated by self-assembly technology. A two-step anodization process was also carried out to obtain templates with pores perpendicular to the substrate without removing the aluminum and barrier layer. Polycrystalline structure was observed with a grain size of about 2 μm in which the pores were almost perfect hexagonally ordered. The pore arrays exhibit different orientation along the boundaries of neighboring grains. Nanopatterning implemented by electron-beam lithography demonstrates the ability to write pores forming concentric circles with pore diameter as small as 50 nm.     

基于动态曝光的激光光刻机的设计

为了提高激光全息防伪技术,开发了以工业控制计算机为上位机、DSP TMS320F2812为下位机的高速光刻机。该光刻机采用动态曝光的工作方式,实现了高速高精度定位。解决了传统光刻机需要在静止的状态下完成曝光的工作模式,使光刻速度提高了20~30倍,提高了激光防伪商标母板制作的技术水平。     

Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below

The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industry-wide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industry's growth. Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL - an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.     

用软光刻技术实现微细结构

本文介绍了一种新的微结构制造技术———软光刻技术 ,它提供了一种方便、有效的和低成本的微米、纳米尺寸微结构的制造方法 .本文着重涉及了软光刻的几项关键技术 :弹性印模、再铸模等 ,阐述了模板的制备方法和原理 ,并应用这种模板实现微阀和微毛细管     

微系统技术（连载三）—光刻工艺

简要介绍邓“三色”双光掩膜光刻工艺,廉价一步光刻方法和阴影投射光刻工艺。     

New test paradigms for yield and manufacturability

As CMOS technology continues its trend down the technology nodes through 90 nm to 14 nm, our industry faces the challenge of achieving necessary yield as we integrate more on-chip circuitry having more complex, advanced process technologies. These technologies are generally less scalable than in the past, which means we're involved in a completely new yield ramp almost every two years. Closing the loop from semiconductor manufacturing back to design and process development is crucial. The author explored the nanometer-era semiconductor yield challenges, classified the yield limiting problems, and discussed how to close the loop back to design and process development. This analysis, summarized in this perspectives, reveals the key role of test and the data it generates to optimize semiconductor yield for the next generation.     

用于光刻系统仿真的多边形处理算法

为提高光刻仿真效率,通过对光刻原理进行研究,提出了2种多边形处理算法,将掩模上的多边形图案进行切分优化,将其划分成若干矩形或三角形。在Linux环境下应用C语言设计出一个完整的光刻仿真系统,设计的具体光学参数为:光源波长为193nm,数值孔径为0.3~0.8,部分相干系数可调范围为0.2~0.8,可一次性仿真1μm×1μm到10μm×10μm范围内的45 nm~0.18μm工艺的复杂版图,并通过多次实验进行验证。实验结果表明:原版图图像的边缘细节得到保留,且该算法有效地减少了光刻模拟的计算复杂度与计算时间,整体效率提升20%以上,为当前智能传感器系统芯片的制造节省了宝贵时间。     

Design and fabrication of a SU-8 based electrostatic microactuator

Comb-drive microactuator is widely used in MEMS devices and traditionally is made of silicon as structural material using silicon-based fabrication technology. Recent development in UV lithography of SU-8 has made it possible to fabricate the ultra high aspect ratio microstructures with excellent sidewall quality. In this paper, we report a low cost alternative to the silicon-based comb drive by using cured SU-8 polymer as structural material. The microactuator was designed to have a integrated structure without assembly or bonding. A unique integration fabrication process was successfully developed based on UV lithography of SU-8 and selectively metallizing SU-8 polymer structures. Preliminary experimental results have proved the feasibility of the microactuator and the fabrication technology.     

SVM based layout retargeting for fast and regularized inverse lithography

Inverse lithography technology （ILT）, also known as pixel-based optical proximity correction （PB-OPC）, has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine （SVM） based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT （LSB-ILT） algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively.     

Spin valve sensors for ultrasensitive detection of superparamagnetic nanoparticles for biological applications

We present giant magnetoresistance (GMR) spin valve sensors designed for detection of superparamagnetic nanoparticles as potential biomolecular labels in magnetic biodetection technology. We discuss the sensor design and experimentally demonstrate that as few as approximately 23 monodisperse 16-nm superparamagnetic Fe(3)O(4) nanoparticles can be detected by submicron spin valve sensors at room temperature without resorting to lock-in detection. A patterned self-assembly method of nanoparticles, based on a polymer-mediated process and fine lithography, is developed for the detection. It is found that sensor signal increases linearly with the number of nanoparticles.