Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

基于40 nm CMOS工艺的电荷泵锁相环设计

本文基于SMIC40nmCMOS工艺,设计了一款输入频率范围25～20MHz,输出频率范围2.4～4GHz的电荷泵锁相环(CPPLL).介绍了电荷泵锁相环的整体电路框架,叙述了各子模块电路的设计、仿真验证与整体电路的设计与仿真验证,重点介绍压控振荡器的设计与仿真优化.版图后仿真结果表明,电荷泵电流失配在直流情况下达到0.3％@0.4-1.3 V;压控振荡器的输出频率范围为0.3～4 GHz、在输出频率1 MHz时相位噪声为-93.4 dB@1MHz、锁定时间为1 μs、绝对抖动为1 ps、典型值时的功耗为30 mW、面积为300×300 μm.     

Reduction of current mismatching in the switches-in-source CMOS charge pump

In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-μm CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.     

Ultra low-voltage CMOS current mirrors

In this paper we present an ultra low-voltage bidirectional and continuous time current mirror based on clocked semi-floating-gate transistors. The current mirror may be used with supply voltages down to 250 mV and frequencies up to several hundred MHz. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm TSMC CMOS process.     

一种降低电源峰值电流的电荷泵电路

为了降低电荷泵电路启动过程中的峰值电流,本文提出了一种具有低峰值电流的电荷泵电路。该电路中采用N-相位时钟电路,产生N个相位不交叠的时钟信号,使得电荷泵启动过程中时钟电路仅对一个电容进行充放电,从而有效减少了电源峰值电流。Hspice仿真结果表明,电荷泵电路级数为4时,所提出的电路能够将电源峰值电流减少约50%。     

辐照诱发CMOS电路器件间漏电流的理论研究

应用解析分析和TCAD器件模拟研究了CMOS电路中由辐照诱发的器件间漏电流问题。以往报道中对于场氧化层中陷阱电荷沉积进而导致寄生漏电流通道开启的物理过程存在若干不同观点,本文中针对这些矛盾点入手,在理论分析中考虑电场强度、氧化层厚度和掺杂浓度随深度的变化,而不仅仅是针对单一变量进行分析。在所有可能的器件间漏电流通道中,以N型阱作为漏区和源区的寄生结构在源漏间存在电压差时相对其他寄生结构对总剂量效应更敏感。但考虑到电路实际工作中N阱区通常接相同电源电平,所以该类寄生结构不会恶化实际CMOS电路的总剂量效应敏感性。总的来说,存在于实际电路中、并且在实际工作中仍然需要考虑的器件间漏电流通道对总剂量效应并不十分敏感（< pA）。     

On-chip high voltage charge pump in standard low voltage CMOS process

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 /spl mu/m CMOS process is presented. For a 250 k/spl Omega/ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.     

Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal

A low-voltage pseudo-differential double-sampled track-and-hold circuit with low hold pedestal based on the Miller-effect scheme is proposed. Rail-to-rail operation of bootstrapped switches allows the low-voltage T/H circuit implementation. Simulation results confirm that the proposed circuit is effective in low-voltage applications with low hold pedestal.     

Ultra-low-voltage SOI CMOS inverting driver circuit using effective charge pump based on bootstrap technique

A novel SOI CMOS inverting driver circuit is reported using a concise charge pump based on bootstrap technique (CPBT) for ultra-low-voltage (ULV) VLSI applications. The ULV driver with CPBT composed of a bootstrap capacitor, a pre-charge device and a driver device, provides a four times speed improvement as compared to a counterpart circuit using the direct bootstrap technique at an output load of 100 fF operating at 0.5 V.     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

锁相环频率综合器中高性能电荷泵设计

本文基于0.18μm CMOS工艺设计并实现了一种新的高性能电荷泵电路。采用宽输入范围的轨到轨运算放大器和自偏置共源共栅电流镜技术提高了电荷泵在宽输出电压范围内的电流匹配精度;同时,提出通过增加预充电电流源技术来提高电荷泵的初始充电电流,以缩短CPPLLs的建立时间。测试结果表明电荷泵在0.4～1.7V输出电压范围内失配电流小于0.4%,充电电流为100μA,预充电电流为70μA。在1.8V电源电压下,电荷泵电路锁定时的平均功耗为0.9mW。     

一种低功耗射频CMOS电荷泵锁相环的设计

CMOS电荷泵锁相环的应用越来越广泛,这也加强了人们该内容的研究与分析。过去,受各方面技术原因的限制,CMOS电荷泵锁相环在具体应用过程中的能量消耗较大,这对其应用造成了一定的不良影响,而近几年随着各项技术的逐渐成熟,人们加强了对低功耗射频CMOS电荷泵锁相环设计的研究,从而满足低功耗、快速锁定要求。目前,人们在该项内容的研究上已经取得了一定的成绩,但是与期望的标准还存在一定差距。文章研究了一种低功耗射频CMOS电荷泵锁相环的设计。     

Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

A regulated body-driven CMOS current mirror for low-voltage applications

A CMOS current mirror (CM) based on the body-driven technique and active feedback scheme is presented. The proposed CM is immune to the threshold voltage limitation and offers much higher accuracy over wider current operating range than other body-driven CMs. The complete analysis of the input-output characteristics, system dc current transfer error, frequency, and noise performance is provided. By using a 1.5V/1V single power supply and 0.18-/spl mu/m n-well process, SPECTRE simulation results validate the analytical results and the overall good performance in terms of wider input-output voltage swing, lower input resistance, and larger output resistance compared with the conventional high-swing cascode CM.     

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

A decoupling circuit using an operational amplifier is proposed to suppress substrate crosstalk in mixed-signal system-on-chip (SoC) devices. It overcomes the parasitic inductance problem of on-chip capacitor decoupling. The effect of the proposed decoupling circuit is not limited by parasitic fine impedance. A 0.13-/spl mu/m CMOS test chip showed that substrate noise at frequencies from 40 MHz to 1 GHz was incrementally suppressed by sequentially activating three of the proposed circuits in parallel. The power dissipation of each circuit was 3.3 mW at a 1.0-V power supply. The test chip measurement showed that the proposed decoupling reduced crosstalk by 31% at 200 MHz, whereas it was reduced by 4.4% with capacitor decoupling. This 7:1 ratio, or 17 dB, corresponds to the gain of the opamp. Design of the opamp and its feedback loop for active decoupling is simple, making the opamp useful for SoC applications.     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.