Chemical mechanical polishing of polymer films

Strategies to reduce capacitance effects associated with shrinking integrated circuit (IC) design rules include incorporating low resistivity metals and insulators with low dielectric values, or “low-κ” materials. Using such materials in current IC fabrication schemes necessitates the development of reliable chemical mechanical polishing (CMP) processes and process consumables tailored for them. Here we present results of CMP experiments performed on FLARE™ 2.0 using a specialized zirconium oxide (ZrO₂) polishing slurry. FLARE™ 2.0 is a poly(arylene) ether from AlliedSignal, Inc. with a nominal dielectric constant of 2.8. In addition, we provide insight into possible removal mechanisms during the CMP of organic polymers by examining the performance of numerous abrasive slurries. Although specific to a limited number of polymers, the authors suggest that the information presented in this paper is relevant to the CMP performance of many polymer dielectric materials.     

砷化镓抛光片总厚度变化研究

抛光片表面总厚度变化是衡量砷化镓抛光片表面质量的重要几何参数指标 ,对后序的器件工艺及集成电路工艺有着至关重要的影响。通过对影响总厚度变化的抛光液组分进行实验分析 ,在抛光工艺中采用化学机械抛光的方法抛出合格的双面抛光片 ,采用统计的方法对测得的总厚度变化数据进行分析 ,找出合适的抛光工艺     

300mm硅片化学机械抛光技术分析

化学机械抛光是单晶硅衬底和集成电路制造中的关键技术之一,然而,传统的化学机械抛光技术还存在一定的缺点或局限性,为了得到更好的硅片平整度和表面洁净度,在300mm硅片的生产中采用了双面化学机械抛光技术.对双面化学机械抛光的优点以及系统变量对抛光速度和抛光质量的影响进行了详细地分析.     

CMP设备控制软件的模块规划及可视化技术

CMP(Chemical Mechanical Polishing)设备是半导体集成电路(IC)制造中的关键设备,CMP设备控制软件的开发是CMP设备研发的关键技术之一。针对三工位CMP机床,自行设计开发了具有抛光压力在线监控、真空吸盘的真空度实时监测、抛光头及抛光盘变频电机转速和转向控制以及机床动作控制等功能的设备监控系统。采用面向对象的方法,给出了监控系统软件模块的划分方法,并对控制功能模块进行了类的封装,重点介绍了多视图通讯的实现以及利用OpenGL实现软件可视化的CMP软件开发关键技术。     

硅通孔抛光液的研究进展

硅通孔(TSV)技术是一种先进的封装技术,化学机械抛光(CMP)是集成电路TSV制作过程中的重要步骤之一,是可兼顾材料表面局部和全局平坦化的技术。抛光液是影响抛光表面质量和加工效率的关键因素,是CMP工艺中消耗品成本最大的部分。TSV抛光液主要包括铜膜抛光液和阻挡层抛光液,依据抛光速率和抛光质量(表面粗糙度、碟形坑修正等)的要求对其进行了分类讨论,概述了近年来TSV抛光液的研究进展,对其今后的研究重点和发展趋势进行了分析和预测,认为TSV抛光液应朝着抛光速率和抛光质量的优化、低成本、环境友好的方向发展。     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

化学机械抛光中的硅片夹持技术

目前半导体制造技术已经进入0.1 3μm时代,化学机械抛光(CMP)已经成为IC制造中不可缺少的技术.本文描述了下一代IC对大尺寸硅片(≥300mm)局部和全局平坦化精度的要求,介绍了目前工业发达国家在化学机械抛光加工中硅片夹持技术方面的研究现状,分析了当前硅片夹持技术中存在的问题,并指出了未来大尺寸硅片超精密平坦化加工中夹持与定位技术的发展趋势.     

GLSI多层布线钨插塞CMP表面质量的影响因素分析

随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对IC工艺中的全局平坦化提出了更高的要求。在特大规模集成电路(GLSI)多层布线化学机械抛光(CMP)过程中,抛光质量对器件的性能有明显影响。研究了多层互连钨插塞材料CMP过程中表面质量的影响因素及控制技术,分析了抛光过程中影响抛光质量的主要因素,确定了获得较高去除速率和较低表面粗糙度的抛光液配比及抛光工艺参数。     

Investigation on the controllable growth of monodisperse silica colloid abrasives for the chemical mechanical polishing application

With the rapid development of chemical mechanical polishing technique as well as its increasing application in IC foundry, the abrasives of slurry are required to have different specifications in terms of size and size’s distribution, which play a vital role in the material removal and defect control. In this study, we monitor in detail the growth process of colloidal silica abrasives changing from the tiny nuclei to large nanoparticles by means of the electron microscopy images. Using the procedure we develop, we are capable of producing monodisperse colloidal silica nanoparticles ranging from 60 to 130 nm in diameter, which are mostly often applied as abrasives in chemical mechanical planarization/polishing (CMP) process of integrated circuit (IC) manufacturing. The physicochemical properties of the silica synthesized by our procedure are also characterized by the X-ray diffraction (XRD) patterns and thermal analysis. The polishing test adopting the colloidal silica as abrasives is performed on silicon wafer to evaluate the CMP properties.     

Characterization and modeling of oxide chemical-mechanicalpolishing using planarization length and pattern density concepts

Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability to reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation in polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical pattern dependent model of the CMP process, integrated with a parameter extraction and process characterization methodology, has been developed to enable accurate and efficient prediction of post-CMP oxide thickness across patterned chips. In the characterization phase, test wafers are polished to obtain model parameters for the desired CMP process. Standard test layouts have been defined which consist of regions with different feature density and pitch; a new contribution is the inclusion of "step density" structures which provide large abrupt post-CMP thickness variations to improve parameter extraction. The key extracted parameter which characterizes the particular CMP process is the planarization length     

CMP系统中抛光头与抛光台运动关系分析

目前半导体制造技术已经进入0.13μm、300mm时代,随着硅片尺寸的增大以及特征线宽的减小,作为目前硅片超精密平坦化加工的主要手段-化学机械平坦化,已经成为IC制造技术中不可缺少的技术。介绍了在化学机械抛光过程中,可以通过抛光头与抛光台运动速度关系优化配置,降低晶片表面不均匀度,从而更好地实现晶片局部和全局平坦化。     

CMP加工中的真空吸盘区域压力控制技术

目前半导体制造技术已经进入0.13μm时代,化学机械抛光(CMP)已经成为IC制造中不可缺少的技术。根据下一代IC对大尺寸硅片(≥300mm)面型精度和表面完整性的要求,分析了CMP(化学机械抛光)加工中大尺寸硅片夹持的关键之一—区域压力控制技术穴ZoneBackPressureControl雪,介绍了采用区域压力控制技术的必要性和理论基础,以及国内外研究现状和最新进展,并指出了该技术存在的问题与发展趋势。     

低压力Cu布线CMP速率的研究

采用低介电常数材料(低k介质)作为Cu布线中的介质层,已经成为集成电路技术发展的必然趋势.由于低k介质的低耐压性,加工的机械强度必须降低,这对传统化学机械抛光(CMP)工艺提出了挑战.通过对CMP过程的机理分析,提出了影响低机械强度下Cu布线CMP速率的主要因素,详细分析了CMP过程中磨料体积分数、氧化剂体积分数、FA/O螯合剂体积分数等参数对去除速率的影响.在4.33 kPa的低压下通过实验得出,在磨料体积分数为20%,氧化剂体积分数为3%,FA/O螯合剂体积分数为1.5%时可以获得最佳的去除速率及良好的速率一致性.     

SiLK dielectric planarization by chemical mechanical polishing

As the feature size of integrated circuits is driven to smaller dimensions the importance of the inter- and intralayer isolator capacitance in future metallization schemes becomes more pronounced. Organic polymers with low dielectric constants are one class of material choice for the replacement of SiO₂. However, their successful integration into functional circuits requires new fabrication procedures. The embedded dielectric scheme offers an evolutionary path for their successful integration into a subtractive etched, aluminum-based integrated circuit. This scheme can effectively lower the total capacitance while minimally changing the rest of the metallization fabrication process. However, the non-conformal deposition of spin-on polymers requires an effective planarization process. Therefore, this paper focuses on the planarization capability of a chemical mechanical polishing process (CMP) using SiLK resin as the interlayer dielectric material. The experimental results demonstrate the high planarization capability of the CMP process using a commercially available slurry. The post-CMP degree of planarization is greater than 95% for all feature dimensions and this planarity can be achieved rapidly. SiLK dielectric coatings are therefore considered as a promising candidate to replace SiO₂ in existing Al/W-based technologies.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

镁合金抛光机理与CMP工艺研究

将化学机械抛光(CMP)技术引入到镁合金片(MB2)的抛光中,打破过去镁合金以单一化学或机械加工为主的加工手段,用自制的抛光液对镁合金片进行抛光实验。结果发现,抛光液中加入双氧水易产生胶体,不利于抛光的进行,因此提出无氧化剂SiO2碱性抛光。同时分析了镁合金的抛光机理,抛光中压力、转速和抛光液流量参数对抛光过程的影响,利用Olympus显微镜对抛光前后镁合金表面进行观察,通过合理控制工艺参数,能够得到较佳的镁合金抛光表面,远优于单一的机械加工,为镁合金抛光工艺和进一步研究抛光液的配比奠定了基础。     

磷化铟的化学机械抛光技术研究进展

磷化铟单晶作为一种重要的外延层衬底材料被广泛应用于光电器件.衬底外延生长和电子器件制备要求磷化铟晶片表面具有极低的表面粗糙度、无表面/亚表面损伤和残余应力等,需对磷化铟晶片表面进行抛光加工,其表面质量决定了后续的外延层质量并最终影响磷化铟基器件的性能.综述了磷化铟晶体化学机械抛光(CMP)技术进展;介绍了磷化铟表面的化学反应原理、CMP去除机理;详细分析了磷化铟抛光液组分及pH值、抛光工艺参数(抛光压力、抛光盘转速、抛光垫特性、磨料种类、粒径及浓度)等对磷化铟抛光质量的影响;介绍了磷化铟抛光片的清洗工艺,并对磷化铟CMP的后续研究方向提出一些建议.     

化学机械抛光浆料研究进展

化学机械抛光(CMP)作为目前唯一可以实现全面平坦化的工艺技术,已被越来越广泛地应用到集成电路芯片、计算机硬磁盘和光学玻璃等表面的超精密抛光.介绍了CMP技术的发展背景,以及目前国内外抛光浆料的研究现状,并根据CMP浆料磨料的性质,将其分为单磨料、混合磨料和复合磨料浆料,对每一种浆料做了总体描述.详细介绍了近年来发展的复合磨料制备技术及其在CMP中的应用,并展望了CMP技术的发展前景以及新型抛光浆料的开发方向.     

陶瓷衬底的化学机械抛光技术研究

介绍了薄膜集成电路陶瓷衬底的化学机械抛光技术,概述了化学机械抛光原理和设备,讨论分析了影响陶瓷衬底的化学机械抛光的因素,并用实验加以验证。     

Rapid characterization and modeling of pattern-dependent variationin chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role