多电平逆变器分析与仿真

目前,多电平逆变器常采用电力电子开关器件串联的逆变器,或者功率单元串联叠加的级联式逆变器.两者不仅直流供电电源不同,电路的结构形式也不同.新型级联多电平逆变器不仅结构简单,而且在输出电平数相同时,所需开关管较少,具有良好的工业应用前景.通过分析典型逆变器结构,阐述其结构特点与联系,并通过软件仿真,比较冬自的抗缺点,为高电压大容量多电平逆变器的选择提供有益的参考.     

Overdistention operation of cascaded multilevel inverters

In the past decade, the multilevel power converter has transitioned from an experimental concept to a standard product of many medium-voltage drive manufacturers. By utilizing small voltage steps, the multilevel topology offers higher power quality, higher voltage capability, lower switching losses, and improved electromagnetic compatibility over standard topologies. Recently, several researchers have focused on the cascaded multilevel inverter whereby two multilevel inverters are series connected to a motor load by splitting the neutral connection. The resulting performance is exceptional in terms of power quality since the overall number of voltage levels is effectively the product of the two cascaded inverters. This paper demonstrates that it is possible to extend this performance to an even higher number of voltage levels referred to as overdistended operation. This further improves the power quality that is significant in applications that have stringent total harmonic distorsion requirements, such as naval ship propulsion. A new control is introduced for overdistention operation and is validated with computer simulation and laboratory measurements.     

Circuit aspects of multilevel self-commutated inverters

A comparative analysis of the circuits of cell- and bridge-type, high-voltage, multilevel inverters is given.     

采用级联多电平逆变器的混合型有源电力滤波器

针对高电压、大容量有源电力滤波器所存在的投资大、技术实现较为困难等问题,提出一种采用单相全桥逆变器和三相逆变器构成的多电平混合型有源电力滤波器方案。在所提方案中,单相和三相逆变器采用不同的电力电子器件实现,不需要与逆变器级联的变压器,从而可降低装置的体积与成本。对多电平逆变器的控制策略、逆变器直流侧电容器电压选取等进行了分析,并以10kV系统为例进行了参数计算和仿真研究。仿真结果表明所提方案具有结构简单、补偿效果好及适合应用于高电压、大容量的谐波滤波场合等特点。     

Reduced common-mode modulation strategies for cascaded multilevel inverters

This paper presents modulation strategies for cascaded multilevel inverters that substantially eliminate common-mode voltage on the output phases. The paper begins by developing generic multilevel inverter reference waveforms that use only "allowed" space vectors to achieve reduced common-mode voltage. A graphical technique is then proposed that allows various carrier disposition modulation strategies for a diode-clamped inverter to be converted to equivalent modulation of a cascaded inverter for any fundamental reference waveform. This graphical technique is confirmed for both alternative phase opposition disposition and phase disposition equivalent modulation of a cascaded inverter, and is then used to create reduced common-mode modulation strategies for cascaded inverters from their equivalent counterparts for diode-clamped inverters under both continuous and discontinuous switching conditions. The strategies have been confirmed by both simulation and experimental results obtained using a cascaded five-level inverter.     

单元串联多电平逆变器PWM方法比较研究

探讨了几种现有的多电平逆变器的脉冲宽度调制PWM(Pulse Width Modulation)方法,提出了一种多电平最优空间矢量方法,该方法通过选取最优空间矢量确定三相最佳电平组合,得到三相电压实际电平值,从而生成三相PWM控制模式。并与现有的PWM方法进行了比较。仿真结果说明多电平最优空间矢量方法具有开关频率低、总谐波含量低的优点。     

多电平逆变器通用电容电压平衡优化算法

针对二极管箝位型多电平逆变器电容电压难以控制的问题,分析了一种简单的多电平逆变器等效模型,用于预测结点电压偏差,提出了一种多电平逆变器电容电压平衡优化SVPWM(space vector pulse width modulation)算法。该算法通过预测不同开关状态下直流侧结点电压偏差,建立目标函数并对其寻优,在每个开关周期选取最优的开关组合达到结点电压平衡。理论分析和试验结果表明,该算法适用于任意电平逆变器电容电压平衡的控制,解决了三电平逆变器电容电压平衡的问题,但在三电平以上的逆变器受调制度限制。针对三电平以上高调制度下电容电压失衡的原因进行了分析,并给出了解决方法。仿真和实验验证了算法的正确性。     

大容量链式STATCOM的三角载波移相-开关频率最优PWM法控制策略的研究

提出了适用于大容量链式静止无功发生器(STATCOM)的一种新的脉冲控制策略,即三角载波移相-开关频率最优PWM法(PS-SFO-PWM)。这种新的PWM方法兼具三角载波移相PWM法(PSPWM)法和开关频率优化PWM法(SFOPWM)的优点,在不提高开关频率的情况下,实现等效高频载波的效果,并提高了直流电压的利用率。研究了链式多电平逆变器的PS-SFO-PWM技术,给出了PS-SFO-PWM控制方法的基本算法,并以2个H桥串联的5电平链式多电平变换器为例,通过Matlab仿真,验证了方法的正确性。     

Particle swarm optimization for harmonic elimination in multilevel inverters

In this paper, harmonic elimination problem in multilevel inverters with any number of levels is redrafted as an optimization task. A new method based on particle swarm optimization is proposed to identify the best switching angles with the dual objectives of harmonic suppression and output voltage regulation. The advantages of fundamental frequency harmonic elimination and swarm intelligence are combined to improve the quality of output voltage of multilevel inverters. The validity of the proposed method is proved through various simulation results.     

A power line conditioner using cascade multilevel inverters fordistribution systems

In this paper, a power line conditioner using a cascade multilevel inverter is presented for voltage regulation, reactive power (VAr) compensation, and harmonic filtering. The cascade M-level inverter consists of (M-1)/2 H bridges, in which each bridge has its own separate DC source. This new inverter can: (1) generate almost sinusoidal waveform voltage with only one time switching per line cycle; (2) eliminate transformers of multipulse inverters used in the conventional static VAr compensators; and (3) make possible direct connection to the 13.8 kV power distribution system in parallel and series without any transformer. In other words, the power line conditioner is much more efficient and more suitable to VAr compensation and harmonic filtering of distribution systems than traditional multipulse and pulsewidth modulation inverters. It has been shown that the new inverter is especially suited for VAr compensation. This paper focuses on feasibility and control schemes of the cascade inverter for voltage regulation and harmonic filtering in distribution systems. Analytical, simulated, and experimental results show the superiority of the new power line conditioner     

运用遗传算法选择性消除多电平逆变器新拓扑中的谐波

目前,传统的PWM技术和选择性谐波消除问题得到了广泛研究。提出运用遗传算法来选择性消除多电平逆变器新拓扑中的谐波。新拓扑与传统结构相比较有减少开关数量的优势,并且可以把输出电平的数量扩展到任何值,该系统减轻了执行机构的复杂性,缩短了计算时间。对于每一个被要求消除的谐波,如果最优开关切换角存在,搜索过程中,遗传算法都可以找到一组最佳开关切换角。模拟仿真和实验结果都验证了新拓扑适合于不同电平数量的逆变器和不同次数的谐波消除。     

Dynamic performance and control of a static VAr generator usingcascade multilevel inverters

A cascade multilevel inverter is proposed for static VAr compensation/generation applications. The new cascade M-level inverter consists of (M-1)/2 single-phase full bridges in which each bridge has its own separate DC source. This inverter can generate almost sinusoidal waveform voltage with only one time switching per cycle. It can eliminate the need for transformers in multipulse inverters. A prototype static VAr generator (SVG) system using 11-level cascade inverter (21-level line-to-line voltage waveform) has been built. The output voltage waveform is equivalent to that of a 60-pulse inverter. This paper focuses on dynamic performance of the cascade-inverter-based SVG system. Control schemes are proposed to achieve a fast response which is impossible for a conventional static VAr compensator (SVC). Analytical, simulated, and experimental results show the superiority of the proposed SVG system     

Analysis of cascaded multilevel inverters for active harmonic filtering in distribution networks

This paper aims at the investigation of an active power filter (APF) comprised of a transformerless multilevel inverter (MLI) for power conditioning in three-phase three-wire distribution network. The inverter topologies used here are three, five, seven and nine-level. The system configuration mainly involves cascaded MLI structure of APF, generation of compensation filter currents based on instantaneous active and reactive current component (i_d–i_q) method and dc-link voltage regulation using a PI controller. Not many papers focus on the regulation of dc-link capacitor voltage. Here we have proposed the implementation of bacterial foraging optimization (BFO) to extract the gains of PI controller. The proposed work provides improved dc-link voltage regulation, quick prevail over current harmonics and reduction of overall source current THD. Adequate MATLAB/Simulink simulation results are presented for the different cascaded MLIs discussed above. Additionally, the performance has been validated in real-time using Opal-RT Lab simulator considering three different conditions of supply i.e., balanced sinusoidal, balanced non-sinusoidal and unbalanced sinusoidal.     

An overheating‐tolerant space vector modulation algorithm for multilevel inverters

As promising and suitable candidates for high‐power applications, multilevel inverters have become one of the most promising solutions in various applications. However, power switching devices are highly subjected to thermal overheating, which leads to shortened lifetime and reduced reliability. Thermal overheating may result from the degradation of power switching devices due to continuous overloading and power cycling. In addition, degradation and faults in the cooling system of power switching devices may cause thermal stresses as well. A new overheating‐tolerant space vector modulation algorithm is proposed in this paper to alleviate thermal stresses from overheated power switching device. The proposed algorithm relies on using the redundancy property between switching states in multilevel inverters to continuously evaluate a cost function of the junction temperature of the overheated device for all possible switching sequence sets and then selects the optimal switching sequence. In addition, the proposed algorithm preserves the DC‐link capacitor voltage without reduction in the output current of the inverter. The proposed algorithm is general, which can be applied to n‐level inverters. Both simulation and experimental results reveal the efficient performance of the proposed algorithm using a three‐level T‐type inverter as a case study. Accordingly, the lifetime and reliability of the inverter are enhanced considerably using the proposed algorithm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel switching strategy for improving modularity and manufacturability of cascaded-transformer-based multilevel inverters

An efficient switching scheme to equalize the size of transformer is proposed for a multilevel inverter employing cascaded transformers, which have a series-connected secondary. All transformers can be designed with the same size regardless of their position because the maximum magnetic flux imposed on each transformer becomes exactly equal each to each. Therefore, identical full-bridge inverter units can be utilized, thus improving modularity and manufacturability. The fundamental idea of the proposed switching pattern is illustrated and then analyzed theoretically. The validity of the proposed switching strategy is verified by experimental results.     

Characteristics comparison of high‐frequency multilevel inverter connected with filter inverters

This paper presents a characteristics comparison of a high‐frequency multilevel inverter connected with small‐ capacity filter inverters. In general, PWM inverters require a low‐pass filter in order to reduce switching harmonics. However, in the high‐frequency systems such as class D power amplifiers, the cutoff frequency of the low‐pass filter must be set at high frequency. Thus, harmonic distortion of the output voltage is enlarged to a harmful level. Increasing the number of output voltage levels is effective in reducing the harmonic distortion of the output voltage and the low‐pass filter size. The proposed systems consist of a five‐level inverter and several cascade‐connected low‐voltage full bridge inverters without any external DC power sources for filtering the output voltage. The five‐level inverter generates a stepwise waveform with five‐level voltage, and the low‐voltage filter inverter superimposes harmonic components to compensate for the voltage waveform distortion. Therefore, the proposed system can reduce its total switching loss and can increase the number of the output voltage levels. In this paper, the effectiveness of the proposed systems is verified through several experiments. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 161(3): 58–65, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20373     

Opportunities for harmonic cancellation with carrier-based PWM fora two-level and multilevel cascaded inverters

Pulsewidth modulation (PWM) strategies have been the subject of many years of research effort, and the merits of the various alternatives investigated have been argued extensively. In general, it is now accepted that natural or asymmetrical regular sampled PWM with a third harmonic injected or a space-vector centered reference waveform gives the best harmonic performance, with discontinuous modulation having some advantages for higher modulation ratios. This paper uses a general analytical solution for carrier-based PWM to mathematically identify the harmonic cancellation that occurs in various PWM implementations and converter topologies. This solution provides a formal justification for the superiority of natural and asymmetrical regular sampling techniques in eliminating half of their sideband harmonics simply by virtue of their phase leg switching. Then, the use of fundamental reference phase shifting between phase legs to create single- and three-phase 1-1 output voltages is reviewed, and the harmonic cancellation that occurs is identified. One significant result from this analysis is the realization that an odd/triplen carrier/fundamental ratio has no intrinsic harmonic benefit, contrary to the generally accepted wisdom. Finally, opportunities for harmonic elimination in multilevel cascaded inverter systems by carrier phase shifting are investigated, and the optimum phase shift is identified     

HVDC transmission system using multilevel power converters based on dual three-phase two-level inverters

Multilevel converters are now an attractive solution for high-voltage direct-current (HVDC) electrical energy transmission systems. Unlike the well-known two-level voltage source converters, multilevel converters use 3 or more voltage levels or steps per leg to modulate the ac voltages, decreasing voltage distortion and reducing electromagnetic interference. This work presents a HVDC transmission system based on a new multilevel structure using a dual two-level converter topology. This structure attains multilevel operation and advantages using two well known three-phase voltage source two-level inverters connected to one three-phase open windings transformer. The proposed dual converter structure has two independent dc links allowing each inverter to process half of the total power. This arrangement is fitted with a control system designed to control the active and reactive power towards their specific set point values, while balancing the voltages of the two dc link capacitors in real time. Obtained results show the effectiveness of the proposed HVDC transmission system.     

Comparison of reduced part count multilevel inverters (RPC-MLIs) for integration to the grid

Multilevel inverters (MLIs) have been developed to a matured level for generating high quality output voltage, used in numerous applications. Conventional MLIs has been received more attention due to their remarkable use in medium-voltage applications. But use of high number of part counts in conventional MLIs increase the intricacy of circuitry and controlling both results in high expenses and reduced reliability. Therefore, development of newer topologies is an active attention to reduce part count compared to the conventional MLIs. This paper presents an exhaustive review of recently proposed reduced part count MLIs for grid integration application on the basis of selection of components, comparative factors and their suitability. It is aimed at presenting a state of the art on configuration, working and their features to researchers, inventors, and application engineers dealing with multilevel inverters.     

A simple unit cell structure for an efficient sketch of series‐connected multilevel inverters

This paper develops a simple design of unit cells to be taken in use in series‐connected multilevel inverters. The proposed structure not only reduces the part counts efficiently but also increases the number of generated levels in the output voltage. By aggregating the cascaded series‐connected units as the basic module, the proposed structure follows one H‐bridge circuit. The basic module acts as the initial stage in direct current/alternative current conversion within which all the positive and zero levels are produced. Afterwards, the H‐bridge circuit affords the production of symmetric sine‐wave by realizing negative levels. To assure the expected operational objectives, we developed three different algorithms to determine the magnitude of input direct current voltage sources. Moreover, to further investigate the proposed structure, different switching algorithms such the fundamental switching frequency and pulse width modulation level shifting approaches are implemented and compared with each other. Extensive numerical and experimental studies are conducted to yield in a suitable evaluation platform. The obtained results demonstrate a superior performance of the proposed structure rather than the conventional topologies. Copyright © 2017 John Wiley & Sons, Ltd.