低k/碳化硅材料与铜互连线的工艺整合

前言对高性能器件的需求使得在半导体制造中推介新型材料的速度大大加快了。事实上，铜、钽基阻挡层、低k电介质以及碳化硅蚀刻停止层等已经以极快的速度相继推出。更低k值的电介质和阻挡层，以及自对准铜帽技术等更多变化将用于下几代器件的制造。可惜的是，半导体业将这些材料整合到生产环境中的能力已经远远落后于设计的需要。在本文中，我们将审视低k材料和阻挡层所带来的对整合工艺的难题，同时我们也将论证如何应对这些挑战。如图1所示，大部分关于整合的难题都出现在原材料之间的界面上。工艺过程引起的损伤具有k值低于3.0的电介质的…     

Cu/低k芯片铜引线键合中应力状态的数值分析

新型Cu/低k芯片以其优异的性能逐步替代Al/SiO2芯片在微纳米器件中得到越来越多的应用。但由于其抗变形能力和强度较低,在引线键合中容易发生损坏。为研究Cu/低k芯片键合中的应力特征和失效机理,建立了Cu/低k芯片与传统Al/SiO2芯片铜引线键合过程的有限元分析模型,计算并对比分析了两种芯片中的应力状态。结果表明:芯片内应力在键合初期快速增长,随后继续增加,但增速变缓;键合过程中高应力区位于铜微球与芯片接触区边缘的下方,呈环形分布;振动中劈刀所在侧高应力区的范围及应力值明显大于另一侧;Cu/低k芯片中应力主要集中于Cu/低k层,Al/SiO2芯片中应力主要集中于劈刀所在侧的Si基板内。键合过程中应力在Cu/低k层的高度集中是新型芯片更易发生分层和开裂失效的根本原因。     

低k介质材料的去胶工艺

据《国际半导体》杂志 1 999年第 2 2卷第 1 2期报道 ,由Ｅａｔｏｎ半导体设备经营管理公司的Ｆｕｓｉｏｎ系统部和ＤｏｗＣｏｒｎｉｎｇ公司联合为 0 1 8μｍ工艺技术开发一种等离子去胶工艺。该课题的最终目的是开发一种全干法等离子去胶工艺 ,对ＨＳＱ低ｋ介质材料上的光刻胶进行高选择性灰化 ,使ＨＳＱ基ＦＯｘ低ｋ薄膜没有“通孔病” (Ｖｉａｐｏｉｓｏｎｉｎｇ) ,以便在 0 1 8μｍ技术中替代ＳｉＯ2 薄膜。低k介质材料的去胶工艺@石松     

低k介质与铜互连集成工艺

阐明了低k介质与铜互连集成工艺取代传统铝工艺在集成电路制造中所发挥的关键作用。依照工艺流程,介绍了如何具体实现IC制造多层互连工艺:嵌入式工艺、低k介质与平坦化、铜电镀工艺与平坦化;阐述了工艺应用现况与存在的难题,给出了国际上较先进的解决方法。     

灵敏低k材料与铜兼容的去胶机

一种成功的抗蚀剂和刻蚀残渣去除胶机必须满足大批量IC制造环境中可接受的3个条件:(1)与灵敏低K介质材料的兼容性;(2)去除抗蚀剂和刻蚀残渣;(3)与基质金属包括铜、钴、钨等金属的兼容性。而AirProdul公司的EZ系列去胶机成功地满足了这些要求。一些含氟化物的产品与灵敏的低k介质,例如多孔的低k材料、HSQ和其它超低k材料是能够很好共处的。对由测量刻蚀速率以及键合保留物和暴露于这些除胶机的覆盖膜组成的介质材料确定的兼容性进行了评价,并对作图衬底的浸泡试验所确定的清洗效力也一并进行了评价。     

低k材料的化学机械抛光研究

阐述了低k材料在IC电路中的作用及其性质,以SiO2、SiOF、SiOCSP、SiOCNSP、Si-OCSO五种材料为研究对象,分析了低k材料与Cu互连工艺的相互联系和作用。在Sikder和Kumar提供的声发射信号(AE)的在线监测图的基础上比较和分析了五种材料的硬度和模数值;根据Preston方程绘制九点测量数据图,发现前三种材料可满足抛光机理,而后两种的抛光行为更倾向于表面反应;根据五种材料抛光前后的实验数据表面形态图表,判断出抛光后材料粗糙度的走向。最后指出低k材料需要发展和完善的工艺及对抛光设备的进一步要求。     

双嵌入式低k介电层/铜工艺技术

介绍了铜／低介电常数介电层的双嵌入式工艺，该工艺已大规模应用于动态记忆存储器（DRAM）和逻辑电路器件中。     

超低k介质材料低损伤等离子体去胶工艺进展

介绍了三类常见的低k介质材料,并对空气隙(k=1)的发展进行了探讨;讨论了引起等离子体损伤的机理和传统的O2等离子体去胶工艺面临的困难;最后综述了近年来国际上提出的低损伤等离子体去胶工艺的研究进展。人们已经开发出一些对低k材料进行硅化处理的工艺,可以部分修复在刻蚀和去胶处理过程中被消耗掉的有机官能团。基于金属硬掩膜层和新型等离子体化学的集成方案将会展示出颇具前景的结果。     

可实现铜及低k技术等离子去胶工艺的湿法清洗技术

用一种顺流微波等离子干法除胶设备开发出了一种享有专利的等离子工艺,该工艺可满足后道工序中铜及低k材料应用中密集和渗透性低k介电材料的抗蚀剂除胶要求。最终结果显示等离子各向同性除胶工艺与其他等离子化学方法相比,在很大程度上可对介电材料的损伤率降到最小,且能实现除胶后的湿法清洗。首先介绍并讨论了在涂覆抗蚀剂片子上得到的综合工艺特征数据。这些数据包括抗蚀剂去胶速率、低k膜厚度损失及折射指数变化、除胶选择性、k值变化、FTIR光谱以及FDS和SIMS分析结果。在有图形的片子上得到的扫描电镜检查结果显示了在等离子去胶和随后的湿法清洗后的清洁度、良好的图形轮廓和图形结构的关键尺寸保持情况。并介绍了评价器件性能的电性能测试和可靠性数据。此外还讨论了等离子工艺在铜表面清洗的有效性。     

0.18μm以下低k介质材料上的低离子等离子体去胶工艺

本文论述了下游式等离子体在多种Cu／低k材料上去胶及去残留物的工艺应用，主要有3类低k材料的实验数据——有机类、掺氮氧化物和多孔性低k材料，同时论述了在这些对应低k材料上新的等离子体气氛：(1)中性等离子体；(2)无氧和还原性等离子体；(3)无氧和无氮等离子体。     

倒装焊器件中Cu/low-k结构热可靠性分析

利用有限元软件建立了倒装焊器件的整体模型和Cu/low-k结构的子模型,分析了在固化工艺及后续热循环条件下Cu/low-k结构的热机械可靠性。结果表明:在金属互连线与低电介质材料的交界处容易产生可靠性问题,采用low-k材料及铜互连线时均增大了两者所受最大等效应力,另外,通孔宽度对low-k及铜线的热应力影响并不明显。     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (t_BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.     

Delamination analysis of Cu/low-k technology subjected to chemical-mechanical polishing process conditions

The mechanical response at the interface between the silicon, low-k and copper layer of the wafer is simulated herein under the loading of the chemical-mechanical polishing (CMP). To identify the possible generation/propagation of the initial crack, the warpage induced by the thin-film fabrication process are considered, and applying pressure, status of slurry and the copper thickness are treated as the parameter in the simulation. Both the simulation and experimental results indicate that the large blanket wafer within high applying pressure would exhibit high stresses possible to delaminate the interface at the periphery of the wafer, and reducing the copper thickness can diminish the possibility of the delamination/failure of the low-k material.     

Numerical Study of Gold Wire Bonding Process on Cu/Low-k Structures

A 2D transient nonlinear finite-element (FE) analysis of thermo sonic wire bonding process on Al-capped Cu/low-k structure is carried out to understand the deformations of bond pad and the responses of structure under bond pad. An FE methodology is established that includes the ultrasonic vibration of the capillary and the analysis is studied at the impacting stage of the wire bonding process. The FE framework allowed for the detailed study of stress evolution in the Cu/low-k structure during the process in order to elucidate the evolved stresses due to the deformation behavior of the bond pad. A comparative study between bonding process on Al-capped and Au-capped low-k structures is also conducted. Effect of variation of frictional coefficients, low-k and undoped silicon glass (USG) modulus and bond pad thickness, on low-k layers and bond pad are investigated to observe their mechanical responses. The effect of implementation of porous low-k material is also highlighted and its presence is shown to increase the sinking of bond pad by a considerable amount. Analysis of the FE calculations together with experimental results suggested some optimal parameters for the bonding process.     

深亚微米下ASIC后端设计及实例

本文通过对传统大规模集成电路设计流程的优化,得到了更适合于深亚微米工艺集成电路的后端设计流程,详细介绍了包括初步综合、自定义负载线的生成、版图规划、时钟树综合、静态时序分析等,并通过前端和后端设计的相互协作对大规模集成电路进行反复优化以实现设计更优。并基于ARTISAN标准单元库,以PLL频率综合器中可编程分频器为例,在TSMC0.18μmCMOS工艺下进行了后端设计,最后给出了可编程分频器的后仿真结果、芯片照片和测试结果,芯片内核面积1360.5μm2,测试结果表明设计符合要求。     

Effective and environmentally friendly remover for photo resist and ashing residue for use in Cu/low-k process

The authors have developed an effective removal solvent for photo resist and its ashing residue for use in copper wire/low-dielectric interlayer devices that significantly lowers the risk of harming the environment. The inhibition of Cu corrosion is very important in these devices, and benzotriazole (BTA, C/sub 6/H/sub 5/N/sub 3/) is usually used as the corrosion inhibitor. However, BTA creates mutagenicity and biodegrades poorly. The authors investigate several typical heterocyclic nitrogen compounds as Cu inhibitors to replace BTA and study their optimum compositions. It has been found that uric acid (C/sub 5/H/sub 4/N/sub 4/O/sub 3/) is the best corrosion inhibitor for Cu. Moreover, this remover, which was composed mainly of amino alcohol, uric acid, and H/sub 2/O, can be applied to low-k films by optimizing its H/sub 2/O ratio. It not only effectively removed the ashing residue on Cu/low-k devices but also effectively reduced the environmental impact because the rinse wastewater containing remover can be completely treated at the fabrication site with ordinary biological processes.     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.     

Cross-Interaction Study of Cu/Sn/Pd and Ni/Sn/Pd Sandwich Solder Joint Structures

Cross-interactions between Cu/Sn/Pd and Ni/Sn/Pd sandwich structures were investigated in this work. For the Cu/Sn/Pd case, the growth behavior and morphology of the interfacial (Pd,Cu)Sn₄ compound layer was very similar to that of the single Pd/Sn interfacial reaction. This indicates that the growth of the (Pd,Cu)Sn₄ layer at the Sn/Pd interface would not be affected by the opposite Cu/Sn interfacial reaction. We can conclude that there is no cross-interaction effect between the two interfacial reactions in the Cu/Sn/Pd sandwich structure. For the Ni/Sn/Pd case, we observed that: (1) after 300 s of reflow time, the (Pd,Ni)Sn₄ compound heterogeneously nucleated on the Ni₃Sn₄ compound layer at the Sn/Ni interface; (2) the growth of the interfacial PdSn₄ compound layer was greatly suppressed by the formation of the (Pd,Ni)Sn₄ compound at the Sn/Ni interface. We believe that this suppression of PdSn₄ growth is caused by heterogeneous nucleation of the (Pd,Ni)Sn₄ compound in the Ni₃Sn₄ compound layer, which decreases the free energy of the entire sandwich reaction system. The difference in the chemical potential of Pd in the PdSn₄ phase at the Pd/Sn interface and in the (Pd,Ni)Sn₄ phase at the Sn/Ni interface is the driving force for the Pd atomic flux across the molten Sn. The diffusion of Ni into the ternary (Pd,Ni)Sn₄ compound layer controls the Pd atomic flux across the molten Sn and the growth of the ternary (Pd,Ni)Sn₄ compound at the Sn/Ni interface.     

The effect of Cu diffusion on the TDDB behavior in a low-k interlevel dielectrics

The effect of Copper on TDDB failure in a structure incorporating a low-k interlevel dielectric was studied theoretically and experimentally. Interdigitated comb capacitor structures were prepared with and without Cu metallization and stressed at 4.0 to 6.6 MV/cm at 150C. The samples without Cu did not fail to over 1800 hours at 4 MV/cm whereas the samples with Cu exhibited a median time to failure (t₅₀) of 45 minutes. At 6.6 MV/cm, the t₅₀ was 1.8 hours for the Cu free samples. This experiment demonstrated the importance of Cu in the TDDB behaviour of low-k dielectrics, but also demonstrated that the presence of Cu was not a necessary condition for failure. The effect of Cu diffusion on TDDB behaviour was studied in the context of the “Impact Damage” model. Both field assisted ionic diffusion and diffusion of neutral Cu was considered. It is seen that the behaviour at low fields near use conditions may have little relationship to the predictions obtained from the results of typical TDDB testing.