An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.     

Process variability-induced NoC link failure: A probabilistic model

As technology scales down, the amount of process variations increases causing Networks-on-Chip (NoC) links, designed to be identical, to have current and delay variations. Thus, some links may fail to meet design timing or power constraints. Using current and delay variations with design constraints, we estimate link failure probability across NoC links. Modeling results show that the average NoC link failure probability across a 4×4 mesh reaches 3.3% for voltage mode (VM) links and 3.7% for current mode (CM) links at 32 nm. The average NoC link failure probability also increases as the supply voltage decreases or the operating frequency increases. As NoC mesh size scales from 4×4 to 8×8, the link failure probability doubles to 8% for VM links at 22 nm. Topology evaluation shows that for small NoC size, the grid topology outperforms the tree one with lower amount of variation. On the other hand, for relatively large NoC sizes, the hierarchical tree and ring topologies outperform the grid topology with lower amount of variations across the links.     

Evaluation of throughput and protection in optically switched metropolitan network architectures

In this study, we investigate the performance of optical packet/burst switched (OPS/OBS) architectures connected as mesh and as ring topologies for future optical metropolitan networks. Network throughput and protection to link failure under uniform traffic distribution for all nodes are investigated to evaluate the sensitivity of OPS/OBSN performance. Our data are based on analytic results and computer simulations that include a comparison between various mesh and ring topologies. We also consider detailed traffic distributions over the network links and the impact caused by failure of more or less loaded links, thus providing a method to select links that require protection, which can be very useful in network planning.     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.     

Secured Self Organizing Network Architecture in Wireless Personal Networks

Secured self organizing network is an approach to computer network architecture that seeks to address the technical issues in heterogeneous networks that may lack continuous network connectivity. In delay tolerant network packets storage exists when there is any link breakage between the nodes in the network so delay is tolerable in this type of network during the data transmission. But this delay is not tolerable in wireless network for voice packet transmission. This evokes the use of wireless networks. In a network, different wireless network topologies are interoperating with each other so the communication across the network is called overlay network. This network is vulnerable to attacks due to mobile behaviour of nodes and frequent changes in topologies of the network. The attacks are wormhole attack and blackhole attack is analysed in this paper. They are critical threats to normal operation in wireless networks which results in the degradation of the network performance. The proposed recovery algorithm for wormhole and the isolation of blackhole will increase the performance of the network. The performance metrics such as throughput, packet delivery ratio, end–end delay and routing overhead of the network are evaluated.

     

DCNC: throughput maximization via delay controlled network coding for wireless mesh networks

Network coding (NC) can greatly improve the performance of wireless mesh networks (WMNs) in terms of throughput and reliability, and so on. However, NC generally performs a batch‐based transmission scheme, the main drawback of this scheme is the inevitable increase in average packet delay, that is, a large batch size may achieve higher throughput but also induce larger average packet delay. In this work, we put our focus on the tradeoff between the average throughput and packet delay; in particular, our ultimate goal is to maximize the throughput for real‐time traffic under the premise of diversified and time‐varying delay requirements. To tackle this problem, we propose DCNC, a delay controlled network coding protocol, which can improve the throughput for real‐time traffic by dynamically controlling the delay in WMNs. To define an appropriate control foundation, we first build up a delay prediction model to capture the relationship between the average packet delay and the encoding batch size. Then, we design a novel freedom‐based feedback scheme to efficiently reflect the reception of receivers in a reliable way. Based on the predicted delay and current reception status, DCNC utilizes the continuous encoding batch size adjustment to control delay and further improve the throughput. Extensive simulations show that, when faced with the diversified and time‐varying delay requirements, DCNC can constantly fulfill the delay requirements, for example, achieving over 95% efficient packet delivery ratio (EPDR) in all instances under good channel quality, and also obtains higher throughput than the state‐of‐art protocol. Copyright © 2014 John Wiley & Sons, Ltd.     

An Efficient and Fair Strategy for Radio Resources Allocation in Multi-radio Wireless Mesh Networks

A Load and Interference aware Resource Allocation strategy (LIRA) is proposed for multi-radio Wireless Mesh Networks (WMNs), combining multiple mechanisms that efficiently optimise radio resources (rate, power and channel) to guarantee max–min fair capacity to every aggregating Mesh Access Point (MAP). LIRA is composed of a rate adaptation and power control mechanism, sensitive to the fat-tree traffic specificities of WMNs, using the highest bit rates at MAP gateways and using, for the ramified links, the minimum ones that satisfy their capacity needs. This enables to efficiently reduce the transmitted power and interference, advantageous for channel reutilisation. LIRA also integrates a load and interference aware channel assignment mechanism, allowing the simultaneous operation of all links without interference. When this is not achievable, two auxiliary mechanisms of channel sharing and interference-free channel reuse can be sub-sequentially used, reducing the capacity of certain MAPs to guarantee fairness to all nodes. LIRA’s gateway flow-control mechanism guarantees that all MAPs respect the allocated capacity, guaranteeing that every MAP is able to operate at its max–min fair capacity. The performance of LIRA is evaluated through simulation, considering IEEE 802.11a. For a classical hexagonal deployment of 19 MAPs with an Internet gateway, it is shown how with only 5 channels LIRA guarantees to every MAP a max–min fair capacity of 3.2 Mbit/s, without packet loss, and delay below 6 ms. It guarantees a max–min fair throughput to every MAP, having a capacity usage efficiency of 66.7 %, an energy efficiency of 26.5 Mbit/J and spectrum efficiency of 0.58 bit/s/Hz. For a more challenging scenario with 27 MAPs and 4 gateways, it is shown how LIRA uses its mechanisms in heterogeneous conditions to also guarantee max–min fair throughput to every MAP, between 5 and 11 Mbit/s, without packet loss, and a delay below 12 ms. Any system improvement will enable to reach higher WMN performance levels using the proposed strategy.     

Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2‐switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non‐uniform traffic models. Results show that the TC‐chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first‐in‐first‐out order of arrivals. The switched delay‐line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright © 2004 John Wiley & Sons, Ltd.     

An experimental study of small multi-hop wireless networks using chirp spread spectrum

Wireless mesh networks have emerged as a viable means of communicating between points that are not within wireless range of each other. There are still, however, a number of challenges involved in designing and implementing such wireless multi-hop networks, particularly with respect to optimising the user throughput. This paper presents some preliminary measurements from an experimental multi-hop wireless networking testbed that has been set up using nodes which utilise Chirp Spread Spectrum (CSS) technology. Multi-hop networks with linear topologies and a maximum of 5 static nodes have been considered. Numerous experiments, mostly indoors, have been performed in which parameters such as the network chain length, the packet size, the logical transmit channel and the transmit power of each node have been varied. The performance of a system with two parallel multi-hop chains was also investigated in which the chains operate simultaneously on either the same or different channels. The end-to-end throughput is observed to fall with increasing chain lengths, typically stabilising for longer chains at values approximately equal to 5–15 % of the single-hop throughput. As the size of the payload is increased, a corresponding linear increase in the throughput is observed. The user throughput also increases with increasing transmit powers at each of the nodes in the chain. However, a trade-off must be made if power and throughput are to be optimised simultaneously.     

Adaptive Priority Sliding Admission Control and Scheduling Scheme for DCF and EDCA WLANs

In this paper an Adaptive Priority Sliding Admission Control and Scheduling (APSAS) scheme is proposed to provide QoS over the existing IEEE802.11 WLANs which operate on Distributed Coordination Function (DCF) and Enhanced Distributed Channel Access (EDCA) mechanisms. The roles of this scheme are generally two folds: (1) To control the number of delay-sensitive real time flows that can be admitted into the WLAN Basic Service Set network and (2) To adjust the priority of selected real time flows in order to accommodate more real time flows without violating the QoS requirement. Extensive simulation studies show that APSAS improves the total throughput, flow throughput ratio, packets end-to-end delay, and jitter of the real time applications when compared with conventional best effort and scheduling-enhanced DCF/EDCA. APSAS also offers near to unity average throughput ratio, lower mean VoIP end-to-end packet delay (<130 ms) and lower mean video packet jitter (<130 ms) over DCF and EDCA.     

GI/Geom/1 queue based on communication model for mesh networks

In mesh networks architecture, it should be permitted to visit the mobile client points. Whereas in mesh networks environment, the main throughput flows usually communicate with the conventional wired network. The so‐called gateway nodes can link directly to traditional Ethernet, depending on these mesh nodes, and can obtain access to data sources that are related to the Ethernet. In wireless mesh networks (WMNs), the quantities of gateways are limited. The packet‐processing ability of settled wireless nodes is limited. Consequently, throughput loads of mesh nodes highly affect the network performance. In this paper, we propose a queuing system that relied on traffic model for WMNs. On the basis of the intelligent adaptivenes, the model considers the influences of interference. Using this intelligent model, service stations with boundless capacity are defined as between gateway and common nodes based on the largest hop count from the gateways, whereas the other nodes are modeled as service stations with certain capacity. Afterwards, we analyze the network throughput, mean packet loss ratio, and packet delay on each hop node with the adaptive model proposed. Simulations show that the intelligent and adaptive model presented is precise in modeling the features of traffic loads in WMNs. Copyright © 2013 John Wiley & Sons, Ltd.     

Mesh IP Video Surveillance Systems Model Design and Performance Evaluation

This paper proposes a model for Internet Protocol (IP) mesh video surveillance systems and presents the performance evaluation of Ah-hoc On-demand Distance Vector (AODV) and Open Shortest Path First (OSPF) routing protocols in wireless mesh video surveillance system. A wireless mesh video surveillance network consists of IP cameras linked to mesh routers which are then linked to the mesh gateways. Local monitoring can be done by inserting a switch or router between the gateways and the Internet while remote monitoring can be done through the Internet. Routing provides selection, constructing and management of routes in order to maximize throughput and minimize video packet losses, end-to-end delays and Jitter. Results show that the OSPF routing protocol outperformed the AODV in throughput, packet loss, end-to- end delay and Jitter terms with a throughput advantage of 35%.     

End-to-End Link Reliable Energy Efficient Multipath Routing for Mobile Ad Hoc Networks

Among the many multipath routing protocols, the AOMDV is widely used in highly dynamic ad hoc networks because of its generic feature. Since the communicating nodes in AOMDV are prone to link failures and route breaks due to the selection of multiple routes between any source and destination pair based on minimal hop count which does not ensure end-to-end reliable data transmission. To overcome such problems, we propose a novel node disjoint multipath routing protocol called End-to-End Link Reliable Energy Efficient Multipath Routing (E2E-LREEMR) protocol by extending AOMDV. The E2E-LREEMR finds multiple link reliable energy efficient paths between any source and destination pair for data transmission using two metrics such as Path-Link Quality Estimator and Path-Node Energy Estimator. We evaluate the performance of E2E-LREEMR protocol using NS 2.34 with varying network flows under random way-point mobility model and compare it with AOMDV routing protocol in terms of Quality of Service metrics. When there is a hike in network flows, the E2E-LREEMR reduces 30.43 % of average end-to-end delay, 29.44 % of routing overhead, 32.65 % of packet loss ratio, 18.79 % of normalized routing overhead and 12.87 % of energy consumption. It also increases rather 10.26 % of packet delivery ratio and 6.96 % of throughput than AOMDV routing protocol.     

Network/hardware cross-layer evaluation for ROHC and packet aggregation on wireless mesh networks

This paper proposes a profile-based network and hardware co-simulation method to investigate the overall performance and real-timing characteristics of a wireless mesh network (WMN) affected by hardware capabilities, speed and complexity. For the sophisticated algorithms to be assisted by a hardware realization, we adopt the RObust Header Compression (ROHC) and packet aggregation that provide high and reliable data transmission over unstable wireless links, which is proven in the preliminary works. To verify the hardware support needs to get the benefit of the two algorithms, we measure the ROHC processing time from Intel Pentium 4 and RouterBOARD, and identify the deterioration of sensor throughput and successful voice calls under various NS-2 simulation scenarios. The co-simulation method integrates the network level simulator, NS-2 and hardware level simulator, SystemC. In this approach, we first insert the modules of ROHC and packet aggregation algorithms into the network simulator hierarchy, and measure the packet arrival times. Then, the corresponding hardware architecture is designed by SystemC for profiling the hardware delay appeared in encoding and decoding packets. The hardware is suitably designed to reduce the complexity and make a sufficient speedup in the packet processing. Finally, the traced hardware delays are applied into the network level simulator to extract real-timing WMN behaviors changed by the hardware operations in each mesh router.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication

Network on chip (NoC) is the solution to solve the problem of larger system on chip and bus based communication system. NoC provides scalable, highly reliable and modular approach for on chip communication and related problems. The wireless communication technologies such as IEEE 802.15.4 Zigbee technology follow mesh, star and cluster tree topology. The paper focuses on the development of machine learning model for design and FPGA synthesis of mesh, ring and fat tree NoC for different cluster size (N = 2, 4, 8, 16, 32, 64, 128 and 256). The fat-tree based topologies incorporate more links near the root of the tree, in order to fulfill the requirement for higher communication demand closer to the root of the tree, as compared to its leafs. It is an indirect topology in which not all routers are identical in terms of number of ports connecting to other routers or elements in the network. The research article presents the use of machine learning techniques to predict the FPGA resource utilization for NoC in advance. The present study helps in NoC chip planning before designing the chip itself by taking into account known hardware design parameters, memory utilization and timing parameters such as minimum and maximum period, frequency support etc. The machine learning is carried out based on multiple linear regression, decision tree regression and random forest regression which estimate the accuracy of the design and good performance. The interprocess communication among nodes is verified using Virtex-5 FPGA, in which data flows in packets and can vary up to ‘n’ bit. The designs are developed in Xilinx ISE 14.2 and simulated in Modelsim 10.1b with the help of VHDL programming language. The developed model has been validated and has performed well on independent test data.     

3D NOC for many-core processors

With an increasing number of processors forming many-core chip multiprocessors (CMP), there exists a need for easily scalable, high-performance and low-power intra-chip communication infrastructure for emerging systems. In CMPs with hundreds of processing elements, 3D integration can be utilized to shorten long wires forming communication links. In this paper, we propose a Clos network-on-chip (CNOC) in conjunction with 3D integration as a viable network topology for many core CMPs. The primary benefit of 3D CNOC is scalability and a clear upper bound on power dissipation. We present the architectural and physical design of 3D CNOC and compare its performance with several other topologies. Comparisons are made among several topologies (fat tree, flattened butterfly, mesh and Clos) showing the power consumption of a 3D CNOC increases only minimally as the network size is scaled from 64 to 512 nodes relative to the other topologies. Furthermore, in a 512-node system, 3D CNOC consumes about 15% less average power than any other topology. We also compare 3D partitioning strategies for these topologies and discuss their effect on wire delay and the number of through-silicon vias.     

A frame-transfer CCD color imager with vertical antiblooming

A high-density 604 (H)× 576 (V) frame-transfer CCD color image sensor is realized with a pixel dimension of 10.0 (H) × 15.6 (V) µm², an image diagonal of 7.5 mm, and a total chip area of 66 mm². On-chip color filters and the use of a triple read-out register result in separate Cy, G, and Ye output signals. The imager is an n-p-n buried-channel CCD which can handle 125 times overexposure with vertical antiblooming. For the calculation of a suitable dopant distribution in the image, storage, and output sections, a four-step procedure has been developed. This procedure has proved to be successful and is much faster than an approach based exclusively on two-dimensional potential calculations.     

A topology preserving cluster‐based channel assignment for wireless mesh networks

Wireless Mesh Networks (WMN) with multiple radios and multiple channels are expected to resolve the capacity limitation problem of simpler wireless networks. However, optimal WMN channel assignment (CA) is NP complete, and it requires an optimal mapping of available channels to interfaces mounted over mesh routers. Acceptable solutions to CA must minimize network interference and maximize available network throughput. In this paper, we propose a CA solution called as cluster‐based channel assignment (CBCA). CBCA aims at minimizing co‐channel interference yet retaining topology through non‐default CA. Topology preservation is important because it avoids network partitions and is compatible with single‐interface routers in the network. A ‘non‐default’ CA solution is desired because it uses interfaces over different channels and reduces medium contention among neighbors. To the best of our knowledge, CBCA is a unique cluster‐based CA algorithm that addresses topology preservation using a non‐default channel approach. The main advantage of CBCA is it runs in a distributed manner by allowing cluster heads to perform CA independently. CBCA runs in three stages, where first the WMN nodes are partitioned into clusters. The second stage performs binding of interfaces to neighbors and third stage performs CA. The proposed algorithm improves over previous work because it retains network topology and minimizes network interference, which in turn improves available network throughput. Further, when compared with two other CBCA algorithms, CBCA provides better performance in terms of improved network interference, throughput, delay, and packet delivery ratios when tested upon network topologies with various network densities and traffic loads. Copyright © 2014 John Wiley & Sons, Ltd.     

分布式队列服务算法在无线网状网包调度中的应用

根据无线网状网的包调度特点,结合已有的差分队列服务算法和分布式贝尔曼-福特算 法,将有线网络中的差分队列服务算法改进为分布式队列服务算法（DQS）,使之实用于无 线网状网中多任务条件下实现系统的吞吐量最大化。仿真实验证明了DQS算法能有效地避免 传统多径传输中的按“类”或 “流”来进行调度的缺陷,有效地减少了数据包的端到端 延时和缓冲区需求,尤其是DQS算法的实际平均吞吐量性能有了很大的提高。