On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.     

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

In this paper, we show the benefits of using asymmetric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% reduction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates.     

高性能微处理器中一种改进的高扇入多米诺电路设计与实现

设计实现了一种改进的高扇入多米诺电路结构.该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管.由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能.在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μw,面积为115μm2.与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.     

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

Investigating the Dynamic Characteristics of High-Temperature SOI CMOS VLSIC Elements

The static and dynamic characteristics of SOI CMOS inverters are investigated in the temperature range from–60 to 250°С. The experimental dependences of the dynamic and static currents, as well as the delay of the logic gate (inverter), on temperature are obtained. Based on these characteristics, the operability of SOI CMOS logic gates at high temperatures is estimated.     

RTD/2-D MESFET logic element for compact, ultra-low-powerelectronics

We describe compact and highly functional logic elements utilizing a two-dimensional (2-D) MESFET with a resonant tunneling diode load. The 2-D MESFET uses two lateral Schottky gate contacts to modulate the width of the 2-D electron gas layer. The novel contact geometry results in reduced gate capacitance, ultra-low-power performance, and the elimination of the Narrow Channel Effect (NCE) compared to conventional HFETs or MESFETs. The advantage of using an RTD as the load device is the reduction of the static power consumption at the logical high input level. We demonstrate low-power RTD/2-D MESFET inverter operation as well as compact NAND and NOR gates using a single RTD/2-D MESFET pair. We also present optimized inverter elements and estimate from SPICE simulations the power-delay products of RTD/2-D MESFET ring oscillators. Compared to recently reported values for CMOS on SOI, the RTD/2-D MESFET technology is expected to exhibit one order of magnitude less active power dissipation and a factor of 3 lower power-delay product     

Femtojoule high speed planar GaAs E-JFET logic

An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

Impact of extrinsic and intrinsic parameter fluctuations on CMOScircuit performance

The yield of CMOS logic circuits satisfying a specific high performance requirement is demonstrated to be significantly influenced by the magnitude of critical-path delay deviations due to both extrinsic and intrinsic parameter fluctuations. To evaluate the impact of these parameter fluctuations, a static CMOS critical-path delay distribution is calculated from rigorously derived device and circuit models that enable projections for future technology generations. Two possible options are explored to attain a desired yield: (1) reduce performance by operating at a lower clock frequency; and (2) increase the supply voltage and, consequently, power dissipation, to satisfy the nominal critical-path delay. For the 50-nm technology generation, the delay and power dissipation increases are 12%-29% and 22%-6%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration. Combining both extrinsic and intrinsic fluctuations, the delay and power dissipation increase to 18%-32% and 31%-53%, respectively, thus demonstrating the significance of including the random dopant placement effect in future CMOS logic designs     

U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ)operation

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate     

A standby current limited performance figure of merit for deepsub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM_max. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM_max technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM_max methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM_max. The value of gate length at which FOM_max occurs decreases with decreasing supply voltage. FOM_max analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic

In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and noise margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the noise margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned noise margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the noise margin. Therefore, this delay model simply relates the speed performance, the power consumption and the noise margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-noise margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

Demonstration of sub-5 ps CML ring oscillator gate delay withreduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT