A low-voltage switched-current delta-sigma modulator

This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm² and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b     

Design techniques for tunable transresistance-C VHF bandpassfilters

In this paper, a tunable wideband linear transresistance (R_m ) amplifier is proposed and analyzed. Using the tunable R_m amplifier, a new transresistance-capacitor (R_m-C) differentiator is designed. Considering the intrinsic capacitances of the MOS transistors as filter elements, this R_m-C configuration can he regarded as a very high frequency (VHF) bandpass biquadratic filter. The proposed biquad has a simple structure and thus occupies a small chip area and consumes little power. Moreover, higher-order VHF bandpass filters can be realized by directly cascading the biquads. Experimental results have successfully proven the capability of the proposed new filter implementation method in realizing VHF bandpass filters with the center frequency higher than 100 MHz when C_d=1 pF. The deviations of the measured center frequency f _o and quality factor Q of the fabricated bandpass filter from the simulated results are less than 8%. The deviation of the center frequency can be post-tuned by adjusting the control voltages V_CN and V_CP of the tunable R_m amplifier. With 1 pF differentiating capacitor, the center frequency of the fabricated VHF R_m-C bandpass filters can be tuned in a wide range larger than 30 MHz. The measured maximum signal level is 25 mV_rms and the dynamic range is 47 dB. The chip area is 0.05 mm² and power consumption is 5.05 mW with ±2.5 V power supply     

Implementing transmission zeros in inductive-window bandpassfilters

Transmission zeros are usually implemented in microwave filters as extracted poles, or with cross couplings between nonadjacent cavities. Recent work, however, indicates that, for inductive band-pass filters, higher order-mode excitation can be usefully exploited for the purpose of creating transmission zeros. In this paper we describe a new cavity configuration that can be used to introduce transmission zeros in the electrical performance of microwave filters based on thick inductive windows in rectangular waveguides using the higher order-mode interactions. One transmission zero per filter cavity can be introduced and its frequency location can be easily controlled adjusting suitable geometrical parameters. The basic principle is discussed in detail and a computer aided design procedure is also presented. Finally, several application examples are included indicating how the new cavity design can indeed be used to improve the performance of this class of filters     

Enhanced switched-current comparator

Practical techniques for accuracy and speed enhancement in switched-current (SI) comparators are presented. Both techniques require minimum added complexity and, more importantly, possess no performance penalty for the comparator in terms of noise and power. Extensive simulations indicate an enhanced SI comparator with an improvement in resolution of >2.5 bit/s and a speed increase of a factor of 1.35 over those of the basic SI comparator. This makes it feasible for the implementation of an SI comparator with >8.5 bit resolution at an operating speed of >270 MHz for a power consumption of <1.7 mW     

New switched-current integrator

A switched-current integrator configuration with greatly improved insensitivity to transistor mismatch is described. A universal integrator configuration is developed which performs an algorithm identical to the well known switched-capacitor universal integrator. This permits signal flowgraph synthesis of switched-current filters with similar properties to those of their switched-capacitor counterparts.<>     

Digitally programmable switched-current FIR filter for low-voltageapplications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 μm CMOS process and operates at a power-supply voltage of 2 V     

Nonlinear switched-current CMOS IC for random signal generation

A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6 mu m CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to approximately 30% of the clock frequency, for a clock frequency of 500kHz.<>     

A switched-current sample-and-hold circuit

A switched-current sample-and-hold circuit is reported. The circuit was fabricated in a 0.8-μm BiCMOS process. Measurements indicate a sampling frequency of 57 MHz with 60 dB signal-to-noise-plus-distortion-ratio and suggest that operation at sampling frequencies beyond 80 MHz is feasible. Comparisons of this circuit with other switched-current sample-and-hold circuits are given to highlight the strengths and weaknesses of the circuit. The feasibility of the sample-and-hold circuit as an under-sampler intended for the Canadian CT2Plus personal communication system is also presented     

High-speed switched-current matched filter for WCDMA receivers

A matched filter (MF) based upon the cascoded class AB SI technique is presented for spread-spectrum communication receivers. Accomplished through both architectural and circuit developments, the filter's features include low power, high speed and compatibility with standard CMOS process inherent to SI signal processing. For performance assessment, a 31-tap 80 MS/s SI MF for despreading task in future high-speed WCDMA receivers is demonstrated.     

Low-voltage fully differential switched-current filters

An accurate high-frequency switched-current integrator based on low-voltage fully-differential folded-cascode current copiers is presented. A five-pole lowpass ladder filter has been integrated using a 1.2 μm n-well CMOS process without floating precision linear capacitors. Experimental results show an accurate filter response for sampling frequencies up to 5 MHz. Using a nominal 3.3 V power supply, the measured dynamic range is 66 dB and the power dissipation is 10 mW/pole     

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

A clock feedthrough reduction circuit for switched-current systems

A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%     

Regulated cascode switched-current memory cell

A new sampled-current signal processing cell is presented. When operated with its memory transistor in saturation it can be designed with high signal swing and low supply voltage. Alternatively, with the addition of a simple clock circuit to produce nearly constant switch charge injection, the memory transistor may be operated in nonsaturation to improve accuracy.<>     

State variable sinusoidal switched-current oscillator

Switched current (SI) is a new analogue sampled-data technique that can be used in place of the switched-capacitor technique, and is very suitable for implementing sampled-analogue functions on VLSI chips. A state variable sinusoidal switched-current oscillator (SIO) is proposed, and is simulated by SPICE.<>     

Programmable switched-current wave analog filters

This paper presents a methodology to realize programmable switched-current filters. A universal wave filter structure is built based on a low-pass (LP) to band-pass (BP) frequency transformation in the z-domain that allows obtaining different filtering functions from a single low-pass reference filter without altering the global circuit topology. Two different parameters, modified by changing the gain of current mirrors, independently control the filter bandwidth and center frequency. A 2.88-mm² IC prototype has been fabricated in a 1.6-μm CMOS digital technology that is capable of implementing three LP's (and their three complementary HP's) and nine BP's (and their nine complementary BR) Chebyschev filters. The realization of the 24 filtering functions requires less than 15% of additional area than that required to implement only one BP function. The chip operates from a 5-V supply, dissipates 0.83 mW/pole, and met the expected performance levels for all filter functions     

A NEW MULTIFUNCTION SWITCHED-CURRENT FILTER

A new switched-current(SI)biquadratic filter is presented which can simultaneouslyprovide the low-pass,high-pass and band-pass filters in a single building block.A symbol torepresent the universal SI integrator is also introduced.It can simplify the analysis and synthesisof SI networks.     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Low-voltage class AB switched-current technique

A low-voltage class AB technique for high-speed and medium-resolution switched-current (SI) signal processing is described. The technique essentially uses the basic class AB SI memory with error-neutralisation and dummy switch schemes to reduce output conductance and charge-injection errors. Simulated results of the balanced class AB memory and bilinear integrator operating at 100 MHz sampling frequency and 1.6 V supply indicates that precision better than 8 bits is entirely feasible over the extreme process and temperature corners