Definition of curve fitting parameter to study tunneling and trapping of electrons in Si/ultra-thin SiO2/metal structures

The tunneling of electrons through metal–oxide–silicon (MOS) structures with ultra-thin oxide is modeled using a linear model for the electron potential energy, an approach which simplifies the computation of both the interface potential and the field penetration distance in the substrate. The one-particle quantum problem is split into finding the metastable states induced by the internal field penetration in the substrate and the running states in the gate region. The two states are assumed to be connected by the condition for the continuity of the probability density at the substrate–dielectric interface. The electron probability current and the total gate current density are obtained for different gate voltages. As the model yields excellent fittings with experimental current–voltage (I–V) data for MOS structures, it was further applied to constant current stressing analysis in order to obtain values for important electron trapping parameters in the oxide. The resultant estimates of the electron trapping cross-section fall in the range of other independent determinations in the literature.     

New positive charge trapping dynamics in SiO2 gate oxide, based on bulk impact ionization processes under Fowler–Nordheim stress

A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO₂) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.     

Hafnium silicate as control oxide in non-volatile memories

SONOS-type MIS capacitors with hafnium silicate as a control oxide are characterized and compared to devices featuring a conventional SONOS gate stack. Write operation is comparable for both gate stack types. Erase operation for the devices with hafnium silicate is improved since the parasitic injection of electrons from the gate is suppressed due to the low electric field in the high-k material. This reduction in leakage current through the gate enhances oxide stability. However, measurements indicate that charge retention for the gate stack with hafnium silicate is degraded for high charge densities. Band bending of the control oxide under high electric fields increases the tunneling probability for trapped charges. Additionally, initial flatband voltage decay is observed due to charge trapping in the hafnium silicate layer. Reducing the thickness of the hafnium silicate layer is possible, maintaining favorable erase properties while minimizing the charge decay rate during retention.     

Charge storage peculiarities in poly-Si–SiO2–Si memory devices with Si nanocrystals rich SiO2

The paper focuses on the study of charge trapping processes in non-volatile memory metal-oxide-silicon (MOS) structures with Si nanocrystal floating gate formed by Si ion implantation. Careful electrical studies of the MOS structures based on the analysis of the capacitance–voltage (C–V) characteristics during pulse charge injection in the oxide enabled the distinguishing of the electron emission from the nanoclusters and the charge trapping in structural defects of the dioxide matrix. The trapping model is discussed.     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.     

Origin of positive charge generated in thin SiO2 filmsduring high-field electrical stress

The characteristics of electron capture in a 131-Å silicon dioxide after hot-hole injection have been studied, which have been compared with those after high-field Fowler-Nordheim (FN) electron injection. After hole injection from the silicon substrate into the oxide, positive charges accumulated in the oxide and electrons could be captured even at low oxide fields only under the positive gate polarity. The charge centroid of the captured electrons was near the substrate-SiO ₂ interface. The low-field electron capture can be explained based on the electron tunneling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO₂ interface. In order to investigate the initial stage of the oxide degradation due to high-field FN stress, electrons were injected from the gate and the charge fluence was selected to be -1.0 C/cm². After the high-field stress, positive charges appeared in the oxide and electrons were captured only under the positive gate polarity by the positive charge and neutral trap centers, which were distributed near the interface. These facts are explained on the basis of the model describing that hole injection and trapping are the dominant causes for the generation of the positive charge centers during high-field FN stress     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Degradation of electron irradiated MOS capacitors

We have investigated the degradation of MOS structure due to high energy electron irradiation as a function of radiation dose and gate bias applied during the irradiation. Devices have been characterized by current–voltage measurements, in order to study charge accumulation also at the gate interface. Three types of oxide charge have been observed: the unstable positive charge, due to trapped holes induced by the electron irradiation; the negative charge in the oxide bulk, deriving from capture of electrons injected during electrical measurements in radiation generated traps; and border traps, at both oxide interfaces.     

High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler–Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel–Poole emission.      

Simulation of substrate hot-electron injection

Electron trapping in thin oxide and interface state generation has been investigated using a constant-current stressing technique. Assuming finite-temperature Fowler-Nordheim tunneling, semiempirical simulations of voltage versus stress time behavior were obtained for an MOS diode. A trapped charge model was used to simulate voltage versus stress-time behavior. The comparison between measurement and simulation results yields information about trapped charges in the oxide and at the oxide-substrate interface. The model can serve as the basis for improved understanding of the more complex phenomenon of channel hot-carrier injection in MOS transistors     

Effect of long-term stress on IGFET degradations due to hot electron trapping

The threshold voltage shift through the long-term stress is measured for IGFET's. The gate bias dependence shows that the hot electron trapping is affected strongly by the electric field in the gate insulator. The threshold voltage shift versus time is well explained with the theory modified by the effect of the trapped charge on the subsequent electron trapping. The effect of transistor dimensions and temperature are also discussed.     

New results on electron injection, hole injection, and trapping in MONOS nonvolatile memory devices

Charge injection and trapping in silicon nitride layers are studied with the three-terminal metal-oxide-nitride-oxide-semiconductor (MONOS) gated-diode structure. A new experimental technique based on the linear voltage ramp is developed which measures electron and hole currents separately in the semiconductor during the actual charge injection (nonsteady-state measurement as opposed to the steady-state method) across the tunneling oxide. In addition, the technique measures the flat-band voltage shift and minimizes the back tunneling of the injected charge (a problem with the pulse measurement). The blocking oxide between the gate electrode and the nitride layer prevents any injection from the gate electrode. The main conclusion from these studies is that the semiconductor injects electrons and holes into the nitride layer for positive and negative polarities of the gate bias, respectively. This result is in sharp contrast with the existing interpretations based on a single-carrier type. It is speculated that the recombination of electrons and holes takes place in the nitride layer via an "amphoteric" trap. At small levels of charge injection, centroids of the trapped charge (measured from the tunneling oxide-nitride interface) for both electron and hole injection conditions are found to be located at 75-80 Å at room temperature and 15-20 Å at 100 K.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.