Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

Calculations of cutoff frequency, breakdown voltage, and capacitance for diffused junctions in thin epitaxial silicon layers

Recent developments in high-quality silicon varactors for low-noise parametric amplifiers and high-efficiency harmonic generators necessitate the use of epitaxial silicon layers that are thinner than 10 microns, with resistivity less than 1 Ω-cm. This paper extends Breitschwerdt's recent calculations [1] to such thin epitaxial layers, and also includes the calculation of series resistance and capacitance per unit area in a range useful for microwave diode design. A planar geometry for the junction has been assumed. The impurity distribution of the in-diffusion from the surface and the out-diffusion from the substrate are assumed to be complementary error functions. Depletion layer characteristics of the p-n junction-- including junction depth, impurity gradient at the junction, depletion layer width, capacitance per unit area, and avalanche breakdown voltage--are predicted for various epitaxial layer resistivities. The capacitance per unit area at breakdown is also presented in graphical form. Series resistance has been obtained by numerical integration of various impurity distributions. Zero-bias cutoff frequency for various layer thicknesses is presented graphically as a function of junction depth and breakdown voltage. The calculations predict that there are optimum diffusion conditions for maximum cutoff frequency and for maximum breakdown voltage with a given epitaxial layer thickness. They indicate that the optimum zero-bias cutoff frequency is nearly inversely proportional to the thickness of the epitaxial layer. For instance, the maximum cutoff frequency of a junction in a 2-µ layer can exceed 600 GHz compared with 300 GHz in a 4-µ layer, and 140 GHz in an 8-µ layer. Calculated and experimentally determined characteristics show reasonably good agreement.     

Optoelectronic devices based on lateral p-n junctions fabricated bymolecular-beam epitaxy growth of silicon-doped GaAs on patterned(311)A-oriented substrates

We demonstrate light-emitting diodes, a vertical-cavity surface-emitting laser (VCSEL), and a photodiode fabricated using a lateral p-n junction. The lateral p-n junction is formed in a GaAs-silicon doped layer grown by molecular-beam epitaxy on a patterned GaAs (311)A-oriented substrate. Lateral p-n junctions have particular properties (i.e., small junction area, coplanar contact geometry, can be clad between electrically insulating layers, allow carrier transport in the plane of multilayer structures, etc.) that are promising for application in new devices. Light-emitting diodes exhibit good electroluminescence at room temperature for both GaAs single layers and GaAs-AlGaAs multiple-quantum-well structures. The VCSEL has electrically insulating distributed Bragg reflectors and coplanar contacts which simplify the device fabrication process. Pulsed-mode operation at room temperature was obtained with a threshold current of 2.3 mA. The light-emission spectrum has a single peak at 942 nm with a full-width at half-maximum of 0.15 nm. The photodiode design allows a reduction of the junction capacitance and an increase of the response speed. A nonoptimized device exhibited a time constant of 10 ps     

Influence of mobility and lifetime variations on drift-field effects in silicon-junction devices

An analysis of devices with drift fields formed by an impurity gradient is carried out allowing for lifetime and mobility variations with impurity concentration. In the case of silicon n-on-p photovoltaic solar cells, a field width of about twice the diffusion length of the minority carriers maximizes the collection efficiency. For lifetimes longer than one microsecond the optimum field width is about 25 µm, a value governed by the absorption characteristics rather than the diffusion length. In most cases, increasing the concentration ratio above 3 orders of magnitude is of little or no assistance in improving the collection efficiency. It is also shown that if the constant relating lifetime to high energy-particle flux is a strong function of impurity concentration, there is little advantage in using drift-field solar cell structures to enhance radiation resistance.     

Flip-chip planar GaInAs/InP p-i-n photodiodes-fabrication andcharacteristics

New flip-chip planar GaInAs/InP p-i-n photodiodes have been fabricated as an array. We describe the structure of the photodiode, the design of a microlens, the fabrication processes, characteristics, and the optical fiber-coupled modules. This photodiode satisfied the requirements for a small junction capacitance and low dark current, good optical fiber coupling, and easy fabrication. We obtained a low dark current with good reproducibility by using two layer polyimide and SiN passivation films. A microlens with a 50 μm φ to 120 μm φ aperture could easily be fabricated with an InP-substrate. By electroplating, flip-chip metal bumps were directly formed on the active region of the photodiode for the first time     

Impact of CdTe/CdZnTe substrate resistivity on performancedegradation of long-wavelength n+-on-p HgCdTe infraredphotodiodes

For realizing HgCdTe focal plane arrays on alternate substrates (Si or GaAs), CdTe buffer layers are essential. Bulk CdTe/CdZnTe substrates are also used for LPE growth of HgCdTe. A model for the effect of the n-CdTe substrate resistivity on the quantum efficiency, η, and the dynamic resistance-area product, R_dA, of a n ⁺-on-p HgCdTe backside illuminated photodiode has been developed, taking into account the effect of the graded heterointerface between CdTe/CdZnTe and HgCdTe on the homojunction photodiode. The issue of how low the substrate/buffer layer resistivity can be, without degrading the performance of the photodiode, has been addressed. For low substrate resistivities, the R_dA can drop by about 50%, while the quantum efficiency decreases by about 5%. It has been found that as low as 2 Ω-cm for long wavelength IR photodiodes (cutoff wavelength 14 μm) is acceptable. To obtain the R_dA and η from the band profile, a linear approximation has been used in which the interface barrier region has a constant electric field, while the bulk of the epilayer has no electric field. General expressions have been derived for the R_dA and η in this two-region model. Our solutions are valid for both high and low electric fields, unlike previously derived solutions in the literature valid either in the one-region low-field case or the two-region, high-field approximation     

漂移区纵向线性掺杂的SOI高压器件研究

随着SOI层厚度的变化,当SOI层的厚度为2μm时,SOI LDMOS器件具有一个最佳的击穿电压.如果漂移区纵向的杂质浓度为线性分布,那么它的纵向电场就会为一个常数,击穿电压会达到最大值,而这种杂质浓度线性分布的漂移区可以通过热扩散得到.采用这种方法制得的SOI LDMOS的纵向击穿电压提高了43%,导通电阻降低了24%,这是因为它的表面浓度更高.     

Planar embedded InP/GaInAs p-i-n photodiode for very high-speed operation

Planar embedded InP/GaInAs p-i-n photodiodes have been fabricated by using preferential ion-beam etching for planarizing and embedding the p-i-n photodiode structure in a semi-insulating InP substrate. The stray capacitances caused by a bonding pad and an interconnection have been markedly reduced, which resulted in extremely low capacitance of less than 0.08 pF for a diameter of 20 μm of photosensitive area. It has been demonstrated by an optical heterodyne technique that the photodiode exhibits a maximum cutoff frequency of 14 GHz. This result was analyzed taking the depletion layer thickness into account and has been found to be dominated by the carrier transit time. The demonstrated low capacitance and high-speed response result indicates the suitability of the p-i-n photodiodes not only for a discrete p-i-n photodiode but also for optoelectronic integration.     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

CMOS图像传感器钳位光敏二极管夹断电压模型研究

A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson＇s equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.     

Maximum Active Concentration of Ion-Implanted Phosphorus During Solid-Phase Epitaxial Recrystallization

In this paper, we showed that the maximum active P concentration of approximately 2 times10²⁰ cm^-3 exists during solid-phase epitaxial recrystallization (SPER). This maximum active concentration is close to the reported values for other active impurity concentrations during SPER. We introduced the concept of an isolated impurity that has no neighbor impurities with a certain lattice range. Assuming that impurities interact with three or four neighbor impurities, we can explain the activation phenomenon during SPER. According to our model, the isolated P concentration N _iso has a maximum value of approximately 2 times10²⁰ cm^-3 at a total impurity concentration of approximately 10²¹ cm^-3, and it decreases with a further increase in total impurity concentration. Deactivation occurs after the completion of SPER with increasing annealing time, and the active impurity concentration decreases with time but is always higher than the maximum diffusion concentration N _{Diff max}. We also observed that N _{Diff max} is independent of the annealing time despite nonthermal activation in the high-concentration region. We evaluated the dependence of N _{Diff max} on annealing temperatures. We think that this N _{Diff max} can be regarded as the electrical solid solubility N _Esol that the active impurity concentration reaches in thermal equilibrium. We observed the transient enhanced diffusion (TED) after the completion of SPER, and that, the deactivation process continues during and after TED, and the corresponding diffusion coefficient is still much higher than that in thermal equilibrium even after TED has finished, which suggests that the deactivation process releases point defects.     

Bandwidth enhancement for p-end-illuminated InP/InGaAs/InP p-i-nphotodiodes by utilizing symmetrical doping profiles

This paper shows that the bandwidth of a p-end-illuminated planar InP-InGaAs-InP heterojunction p-i-n photodiode can be promoted by using a rather symmetrical doping profile that is produced through diffusion depth control. Caused by extra-depleted InP region in the end of p-InP, the device with symmetrical doping profile has additional series capacitance and thus has a smaller total capacitance than conventional asymmetrical doping profile. Such devices with 0.3 μm depleted InP cap region, together with 1 μm depleted InGaAs absorption region and 0.3 μm depleted InP buffer region, having the capacitance as small as those devices with 1.6 μm depletion region, while have the carrier transit time as short as those devices with 1.3 μm depletion region. Under appropriate bias condition, which is required for getting rid of the heterointerface effects, the symmetrical device as stated with 40 μm junction diameter can have a 3 dB bandwidth exceeding 17 GHz without inductance optimization. For device with conventional asymmetrical doping profile, that is, the p-n junction locating at ~0.1 μm deep in the InGaAs layer, only a bandwidth of about 15 GHz can be obtained. Due to the same thickness of InGaAs absorption layer, both devices have similar responsivity of ~0.8 A/W at -5 V at 1.3 μm wavelength. However, the heterointerface exposed in the depletion region results in several detrimental effects in symmetrical devices, such as interface-generation current, which leads to slightly increased dark current, and barrier/traps for hole transport, which lead to inferior photoresponse at low biases     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

Simulation of near-surface proton-stimulated diffusion of boron in silicon

A quantitative model for near-surface redistribution of doping impurity in silicon in the course of proton-stimulated diffusion is developed for the first time. According to the model, the near-surface peak of the impurity concentration is caused by migration of neutral impurity—self-interstitial pairs to the surface with subsequent decomposition of these pairs and accumulation of the impurity at the silicon surface within a thin layer (referred to as δ-doped layer). The depletion and enhancement regions that are found deeper than the near-surface concentration peak are caused by expulsion of ionized impurity by an electric field from the near-surface region of the field penetration. The field appears due to the charge formed in the natural-oxide film at the silicon surface as a result of irradiation with protons. The diffusion-kinetic equations for the impurity, self-interstitials, vacancies, and impurity—self-interstitial pairs were solved numerically simultaneously with the Poisson equation. It is shown that the results of calculations are in quantitative agreement with experimental data on the proton-stimulated diffusion of boron impurity in the near-surface region of silicon.     

Technologies to improve photo-sensitivity and reduce VOD shuttervoltage for CCD image sensors

New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p⁺-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers     

Small-junction-area GaInAs/InP pin photodiode with monolithicmicrolens

Reports on a back-illuminated GaInAs/InP pin photodiode with a monolithic microlens fabricated by the authors. The photodiode has both an ultrabroad bandwidth of 18 GHz and a high quantum efficiency of about 84%. It achieves this by using a small pin junction area while maintaining a large fibre alignment tolerance by incorporating an InP microlens. The photodiode capacitance was 20 fF for a junction diameter of approximately 15 μm     

Photoeffect on diffused P-N junctions with integral field gradients

A detailed analysis of a diffused junction photodiode is presented in which the illumination, monochromatic or broad-band, is applied to the diffused face. The electric field produced by the impurity distribution, assumed exponential, assists the transport and collection of minority carriers created by photons absorbed in the graded region. The theoretical study covers both the steady-state and the transient response, and takes into account the effect of surface recombination velocity. The presence of the built-in field increases the photocurrent and reduces the dark current compared with homogeneous base diodes. For p-n silicon photodiodes with 5-micron base widths and acceptor concentrations of say, 2 × 10¹⁸atoms/cm³at the surface, photosensitivities of approaching 0.01 ampere per lumen may be achieved. The transient-response analysis considers the extrinsic delay imposed by the time constant of the junction capacitance and the load resistance, and also the inherent delay caused by the transit time of the minority carriers. With moderate or high load resistances, the extrinsic delay is much larger than the transit-time delay. However, for comparable graded- and homogeneous-base photodiodes, the capacitances of graded junctions are lower, and therefore the transient response is improved on this account. The graded junctions also are shown to have greatly reduced transit-time delays because of the built-in field effect.     

The feasibility of obtaining general impurity distributions by diffusion

Although it is possible to optimize selected characteristics of semiconductor devices by controlling the net impurity distribution, present methods used for fabricating planar devices by diffusion techniques invariably produce profiles which are approximately either Gaussian or complementary error functions. The purpose of this paper is to examine the feasibility of obtaining a general impurity profile within intrinsic material using diffusion techniques. It is shown that by treating the problem as an optimum control problem, one can, in principle, obtain a best-fit approximation to a given profile by controlling the gas stream impurity concentration. A first-order model is developed to characterize the surface interactions between the gas ambient and the solid; the boundary value problem for diffusion is then solved. A computational routine using linear programming techniques is developed which, for a given diffusion time, determines the necessary control function producing a best-fit approximation to the desired profile over the spatial range of interest. The optimum control functions governing the diffusion of boron in silicon for three given impurity profiles are synthesized: a constant profile, an exponential profile, and the minimum transit time profile. The computational results clearly establish the feasibility of obtaining an approximation to a given impurity profile.     

Dispersion characteristics of diffused channel waveguides

A variational method is used to calculate dispersion curves for channel waveguides fabricated by masked diffusion. Composition profiles for the waveguides are obtained by numerical solution of the diffusion equation, assuming that the diffusant concentration in the unmasked region of the substrate surface is constant during the diffusion process. A linear dependence of refractive index change on diffusant concentration is assumed. The dependence of the number of guided modes on mask gap width and diffusion depth is determined as an aid to the design of modulators and switches for integrated optics.     

High frequency space charge layer capacitance of strongly inverted semiconductor surfaces

The finite spatial extension of the inversion layer minority carriers shunts the dielectric capacitance of the inversion layer and increases the high frequency semiconductor surface space charge layer capacitance in the strong inversion range by about 5 per cent. This distributed minority carrier distribution also gives rise to a small (about 1 per cent) high frequency capacitance minimum near the onset of strong surface inversion. A simple two-lump model is developed which is accurate to within 0·4 per cent of the numerical solution obtained from the exact transmission line model. Applied gate voltages at the capacitance minimum are presented graphically as a function of oxide thickness with the substrate impurity concentration as a parameter. Surface quantization effect is not taken into account.