基于蚂蚁路径的时序电路故障诊断算法

提出了一种VLSI时序电路自动测试型生成(Automatic test pattern generation，ATPG)的新算法。传统ATPG算法采用局部状态转换图或收集门级电路的知识以及提取电路规则来解决时序电路ATPG的困难。本算法引入新的模型，着重解决了ATPG中的计算冗余问题。在蚂蚁路径模型的基础上，前向搜索得到了重建，故障点的前向传输和回溯归结到了单一路径之上．而该路径上可能分布着许多待测的故障点，从而改善了以往时序电路ATPG算法中搜索重复而导致的计算冗余问题，同时，最小测试向量的获取为数学定理所证明。最后在Benchmark电路上进行的与ILP算法的比较试验表明，本算法具备同样的故障覆盖率，且速度更快。     

Forecasting the efficiency of test generation algorithms for combinational circuits

In this era of VLSI circuits,testability is truly a very crucial issue.To generate a test set for a given circuit,choice of an algorithm from a number of existing test generation algorithms to apply is bound to vary from circuit to circuit.In this paper,the Genetic Algorithm is used in order to construct an accurate model for some existing test generation algorithms that are being used everywhere in the world.SOme objective quantitative measures are used as an effective tool in making such choice.Such measurews are so important to the analysis of algorithms that they become one of the subjects of this work.     

Brain Derived Vision Algorithm on High Performance Architectures

Even though computing systems have increased the number of transistors, the switching speed, and the number of processors, most programs exhibit limited speedup due to the serial dependencies of existing algorithms. Analysis of intrinsically parallel systems such as brain circuitry have led to the identification of novel architecture designs, and also new algorithms than can exploit the features of modern multiprocessor systems. In this article we describe the details of a brain derived vision (BDV) algorithm that is derived from the anatomical structure, and physiological operating principles of thalamo-cortical brain circuits. We show that many characteristics of the BDV algorithm lend themselves to implementation on IBM CELL architecture, and yield impressive speedups that equal or exceed the performance of specialized solutions such as FPGAs. Mapping this algorithm to the IBM CELL is non-trivial, and we suggest various approaches to deal with parallelism, task granularity, communication, and memory locality. We also show that a cluster of three PS3s (or more) containing IBM CELL processors provides a promising platform for brain derived algorithms, exhibiting speedup of more than 140 × over a desktop PC implementation, and thus enabling real-time object recognition for robotic systems.     

A Parallel Genetic Algorithm Based on Spark for Pairwise Test Suite Generation

Pairwise testing is an effective test generation technique that requires all pairs of parameter values to be covered by at least one test case. It has been proven that generating minimum test suite is an NP-complete problem. Genetic algorithms have been used for pairwise test suite generation by researchers. However, it is always a time-consuming process, which leads to significant limitations and obstacles for practical use of genetic algorithms towards large-scale test problems. Parallelism will be an effective way to not only enhance the computation performance but also improve the quality of the solutions. In this paper, we use Spark, a fast and general parallel computing platform, to parallelize the genetic algorithm to tackle the problem. We propose a two-phase parallelization algorithm including fitness evaluation parallelization and genetic operation parallelization. Experimental results show that our algorithm outperforms the sequential genetic algorithm and competes with other approaches in both test suite size and computational performance. As a result, our algorithm is a promising improvement of the genetic algorithm for pairwise test suite generation.     

适用于异构集群的混合并行流线生成系统

流线是流场可视化的主要方法之一,而针对大规模流场的流线生成由于计算量大往往需要采用高性能计算机这样的并行计算环境结合并行化算法以实现计算加速.在当前异构计算系统越来越普遍的情况下,为了充分利用并行异构计算环境的计算能力,实现更高效的并行流线生成,本文采用了基于数据并行原语结合分布式消息通讯的技术架构,设计了一套适用于异...     

时序电路测试向量融合算法

时序电路的测试序列通常由各个单故障的测试向量组成.为了减少测试时间和功耗,提出2种测试向量融合算法.借助融合灵活性的概念,2种算法按不同的方式对向量序列进行排序,并以融合深度和代价作为评判准则,构建向量的融合过程,最终生成整个电路的测试序列.该算法与已有的Greedy算法时间复杂度相同,但性能更优.在ISCAS89部分电路上的实验结果表明,采用文中算法可使平均性能分别提高4.96%和8.23%.故障仿真结果表明,文中算法的故障覆盖率有少量提高,故障分辨率变化较小.     

DNA and quantum based algorithms for VLSI circuits testing

Testing of VLSI circuits is still a NP hard problem. Existing conventional methods are unable to achieve the required breakthrough in terms of complexity, time and cost. This paper deals with testing the VLSI circuits using natural computing methods. Two prototypical algorithms named as DATPG and QATPG are developed utilizing the properties of DNA computing and Quantum computing, respectively. The effectiveness of these algorithms in terms of result quality, CPU requirements, fault detection and number of iterations is experimentally compared with some of existing classical approaches like exhaustive search and Genetic algorithms, etc. The algorithms developed are so efficient that they require only N (where N is the total number of vectors) iterations to find the desired test vector whereas in classical computing, it takes N/2 iterations. The extendibility of new approach enables users to easily find out the test vector from VLSI circuits and can be adept for testing the VLSI chips.     

树型网格计算环境下的独立任务调度

任务调度是实现高性能网格计算的一个基本问题,然而,设计和实现高效的调度算法是非常具有挑战性的.讨论了在网格资源计算能力和网络通信速度异构的树型计算网格环境下,独立任务的调度问题.与实现最小化任务总的执行时间不同(该问题已被证明是NP难题),为该任务调度问题建立了整数线性规划模型,并从该线性规划模型中得到最优任务分配方案??各计算节点最优任务分配数.然后,基于最优任务分配方案,构造了两种动态的需求驱动的任务分配启发式算法:OPCHATA(optimization-based priority-computation heuristic algorithm for task allocation)和OPBHATA(optimization-basedpriority-bandwidth heuristic algorithm for task allocation).实验结果表明:在异构的树型计算网格环境下实现大量独立任务调度时,该算法的性能明显优于其他算法.     

Hitest: A Knowledge-Based Test Generation System

Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.     

Efficient strategies for parallel mining class association rules

Mining class association rules (CARs) is an essential, but time-intensive task in Associative Classification (AC). A number of algorithms have been proposed to speed up the mining process. However, sequential algorithms are not efficient for mining CARs in large datasets while existing parallel algorithms require communication and collaboration among computing nodes which introduces the high cost of synchronization. This paper addresses these drawbacks by proposing three efficient approaches for mining CARs in large datasets relying on parallel computing. To date, this is the first study which tries to implement an algorithm for parallel mining CARs on a computer with the multi-core processor architecture. The proposed parallel algorithm is theoretically proven to be faster than existing parallel algorithms. The experimental results also show that our proposed parallel algorithm outperforms a recent sequential algorithm in mining time.     

Effective synchronizing algorithms

The notion of a synchronizing sequence plays an important role in the model-based testing of reactive systems, such as sequential circuits or communication protocols. The main problem in this approach is to find the shortest possible sequence which synchronizes the automaton being a model of the system under test. This can be done with a synchronizing algorithm. In this paper we analyze the synchronizing algorithms described in the literature, both exact (with exponential runtime) and greedy (polynomial). We investigate the implementation of the exact algorithm and show how this implementation can be optimized by use of some efficient data structures. We also propose a new greedy algorithm, which relies on some new heuristics. We compare our algorithms with the existing ones, with respect to both runtime and quality aspect.     

DFSP: a Depth-First SPelling algorithm for sequential pattern mining of biological sequences

Scientific progress in recent years has led to the generation of huge amounts of biological data, most of which remains unanalyzed. Mining the data may provide insights into various realms of biology, such as finding co-occurring biosequences, which are essential for biological data mining and analysis. Data mining techniques like sequential pattern mining may reveal implicitly meaningful patterns among the DNA or protein sequences. If biologists hope to unlock the potential of sequential pattern mining in their field, it is necessary to move away from traditional sequential pattern mining algorithms, because they have difficulty handling a small number of items and long sequences in biological data, such as gene and protein sequences. To address the problem, we propose an approach called Depth-First SPelling (DFSP) algorithm for mining sequential patterns in biological sequences. The algorithm’s processing speed is faster than that of PrefixSpan, its leading competitor, and it is superior to other sequential pattern mining algorithms for biological sequences.     

Parallel Algorithms for Dynamic Shortest Path Problems

The development of intelligent transportation systems (ITS) and the resulting need for the solution of a variety of dynamic traffic network models and management problems require faster‐than‐real‐time computation of shortest path problems in dynamic networks. Recently, a sequential algorithm was developed to compute shortest paths in discrete time dynamic networks from all nodes and all departure times to one destination node. The algorithm is known as algorithm DOT and has an optimal worst‐case running‐time complexity. This implies that no algorithm with a better worst‐case computational complexity can be discovered. Consequently, in order to derive algorithms to solve all‐to‐one shortest path problems in dynamic networks, one would need to explore avenues other than the design of sequential solution algorithms only. The use of commercially‐available high‐performance computing platforms to develop parallel implementations of sequential algorithms is an example of such avenue. This paper reports on the design, implementation, and computational testing of parallel dynamic shortest path algorithms. We develop two shared‐memory and two message‐passing dynamic shortest path algorithm implementations, which are derived from algorithm DOT using the following parallelization strategies: decomposition by destination and decomposition by transportation network topology. The algorithms are coded using two types of parallel computing environments: a message‐passing environment based on the parallel virtual machine (PVM) library and a multi‐threading environment based on the SUN Microsystems Multi‐Threads (MT) library. We also develop a time‐based parallel version of algorithm DOT for the case of minimum time paths in FIFO networks, and a theoretical parallelization of algorithm DOT on an ‘ideal’ theoretical parallel machine. Performances of the implementations are analyzed and evaluated using large transportation networks, and two types of parallel computing platforms: a distributed network of Unix workstations and a SUN shared‐memory machine containing eight processors. Satisfactory speed‐ups in the running time of sequential algorithms are achieved, in particular for shared‐memory machines. Numerical results indicate that shared‐memory computers constitute the most appropriate type of parallel computing platforms for the computation of dynamic shortest paths for real‐time ITS applications.     

Parallel implementation of fuzzy minimals clustering algorithm

Clustering aims to classify different patterns into groups called clusters. Many algorithms for both hard and fuzzy clustering have been developed to deal with exploratory data analysis in many contexts such as image processing, pattern recognition, etc. However, we are witnessing the era of big data computing where computing resources are becoming the main bottleneck to deal with those large datasets. In this context, sequential algorithms need to be redesigned and even rethought to fully leverage the emergent massively parallel architectures. In this paper, we propose a parallel implementation of the fuzzy minimals clustering algorithm called Parallel Fuzzy Minimal (PFM). Our experimental results reveal linear speed-up of PFM when compared to the sequential counterpart version, keeping very good classification quality.     

一种基于QoS的自适应网格失效检测器

失效检测器是构建可靠的网格计算环境所必需的基础组件之一.由于网格中存在大量对失效检测有着不同QoS需求的分布式应用,对于一个网格失效检测器来说,为保持其有效性和可扩展性,应该既能够准确提供应用程序所需的失效检测QoS,又能够避免为满足不同QoS而设计多套失效检测器所产生的多余负载.基于QoS基本评价指标,采用PULL模式主动检测策略实现了一种新的失效检测器--GA-FD(adaptive failure detector for grid),可以同时支持多个应用程序定量描述的QoS需求,不需要关于消息行为和时钟同步的任何假设.同时,证明了GA-FD在部分同步模型下可实现一个◇P类的失效检测器,并给出了相应的实验及数据.     

Mining top-k co-occurrence items with sequential pattern

Frequent sequential pattern mining has become one of the most important tasks in data mining. It has many applications, such as sequential analysis, classification, and prediction. How to generate candidates and how to control the combinatorically explosive number of intermediate subsequences are the most difficult problems. Intelligent systems such as recommender systems, expert systems, and business intelligence systems use only a few patterns, namely those that satisfy a number of defined conditions. Challenges include the mining of top-k patterns, top-rank-k patterns, closed patterns, and maximal patterns. In many cases, end users need to find itemsets that occur with a sequential pattern. Therefore, this paper proposes approaches for mining top-k co-occurrence items usually found with a sequential pattern. The Naive Approach Mining (NAM) algorithm discovers top-k co-occurrence items by directly scanning the sequence database to determine the frequency of items. The Vertical Approach Mining (VAM) algorithm is based on vertical database scanning. The Vertical with Index Approach Mining (VIAM) algorithm is based on a vertical database with index scanning. VAM and VIAM use pruning strategies to reduce the search space, thus improving performance. VAM and VIAM are especially effective in mining the co-occurrence items of a long input pattern. The three algorithms were evaluated using real-world databases. The experimental results show that these algorithms perform well, especially VAM and VIAM.     

Automatic test pattern generation on parallel processors

Test generation for combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of the backtrack search algorithm called PODEM, which is a highly used algorithm for this problem. It is known that the sequential PODEM algorithm consumes most of its execution time in generating tests for ‘hard-to-detect’ (HTD) faults and is often unable to detect them even after a large number of backtracks. Our parallel formulation overcomes these limitations by dividing the search space and searching it concurrently using multiple processes.

We present a number of experimental results and show that these match our theoretical results presented elsewhere. We show that the search efficiency of the parallel algorithm improves and even beats that of the sequential algorithm as the ‘hardness’ of a fault increases. We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. We also present preliminary results on a network of Sun workstations. Our results show that parallel search techniques provides good speedups as well as high fault coverage of the HTD faults in reasonable time when compared to the uniprocessor implementation. Our experimental validation of most of our theoretical results builds confidence in the following theoretical prediction: our parallel formulation of PODEM is highly scalable on a variety of commercially-available, large MIMD parallel processors (in additions to the ones with which we experimented).     

关联规则的序贯抽样算法比较研究

关联规则发现是数据挖掘的核心技术,其中最经典的算法是Apriori算法。Apriori算法创建模型的方法是一次性抽样的方法。这种机器学习中传统而主流的建模技术,通常需要大量的样本量,这无疑会导致算法执行效率低下。最近几年,一些自适应的抽样建模方法逐渐得到重视,其中CarlosDomingo眼3演提出的基于序贯抽样理论的可升级性算法是其中之一,这一方法为用更少的资源建立稳健且不断更新的模型提出了新的思路。文章首先比较序贯抽样算法与传统的一次性抽样算法在关联规则中发现中的不同,接着论述将序贯抽样算法与Apriori算法结合同时达到节省空间和样本量的APASAR算法,最后通过模拟比较三种不同算法的执行效果。     

Computing motion using analog VLSI vision chips: An experimental comparison among different approaches

We have designed, built and tested a number of analog CMOS VLSI circuits for computing 1-D motion from the time-varying intensity values provided by an array of on-chip phototransistors. We present experimental data for two such circuits and discuss their relative performance. One circuit approximates the correlation model while a second chip uses resistive grids to compute zero-crossings to be tracked over time by a separate digital processor. Both circuits integrate image acquisition with image processing functions and compute velocity in real time. For comparison, we also describe the performance of a simple motion algorithm using off-the-shelf digital components. We conclude that analog circuits implementing various correlation-like motion algorithms are more robust than our previous analog circuits implementing gradient-like motion algorithms.     

Design for Testability for Complete Test Coverage

Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.