锁相环中一种特殊的失锁现象分析及解决措施

本文从一种锁相环路失锁现象出发,从理论上分析了出现这种失锁现象的原因,得出了一个结论:反馈支路中加有混频器的所有类型的锁相环路中,均存在一种由于“恶性循环”导致环路失锁的可能性。提出了解决这种失锁的办法,并在实验中证明所用解决办法是行之有效的。     

YIG滤波器的补偿电路设计

介绍了YIG滤波器主要性能及其在应用中所需的驱动电路设计方法,重点介绍了YIG滤波器驱动电路的磁滞、非线性和温度飘移等非理想特性及其补偿与校正方法。     

RC积分滤波(1+K)sinφ/1+Kcosφ鉴相锁相环路捕捉曲线的一个近似公式

<正> 一、引言准确画分参数的捕捉区域,对设计锁相环路是十分必须的。由于环路方程是非线性的,所以一般都不能准确解出,而必须采用各种近似方法给出捕捉曲线。关于线性,三角波,余弦鉴相,已经有一些文章提出了近似结果,本文对具有(1+K)sinφ/1+Kcosφ鉴相特性,RC积分滤波的锁相环路提出一个近似的捕捉曲线近似公式,以期得到实践的验证,并进一步改进。二、方程形式及参数选取考虑固定频率及相位输入的锁相环路方程     

锁相技术在激光测距仪中的应用

本文在简要地叙述了锁相技术的一般概念,激光测距仪中为什么要锁相以及锁相环路的工作原理和技术指标之后,指出了过去激光测距仪锁相环路所存在的缺点,提出了精密激光测距仪JCY-3A型(1号机)中独特的锁相环路,对所使用的锁相环路(新型的鉴相器及环路滤波器)的特点和优点作了分析和描述。文章着重介绍了变带宽法和利用变带宽法所设计的失锁自动恢复电路,并对研制成功的锁相环路的性能和指标作了测试。通过测试和装机实验证明了使用此锁相环路所具有的优点和可靠性。     

利用锁频环路的快速跳频合成信号发生器

介绍一种高性能快速跳频合成信号发生器,利用锁相环路和锁频环路相结合的原理和跳频校准控制技术而实现的。着重介绍了延迟线鉴频器锁频环路的工作原理、低噪声特性和宽带特性,仪器实现低相噪和快速频率转换的机理。介绍了通过信道、序列设置,每个频率点的环路增益参数和预调电压的校准和存储,实现快速跳频的方法。     

基于MuItiSim7的锁相环路研究

文章阐述了锁相环路的相位负反馈控制原理，推导锁相环路线性相位模型的动态方程和传递函数。在Multisim7电路仿真平台上，通过二阶环仿真实例，分析和验证二阶环的频率牵引、捕获、锁定和失锁状态的控制机理，并测量环路快捕带、同步带和稳态相差等指标。     

微波单晶铁氧体器件再展雄风

本文叙述了微波单晶铁氧体器件——YIG调谐滤波器(YTF);YIG调谐振荡器(YTO);YIG调谐器件组件;YIG单晶薄膜及平面器件;磁光器件的概况及其发展方向。 微波单晶铁氧体器件已有近50年发展历史。YIG调谐滤波器(YTF),YIG调谐振荡器(YTO)是其典型产品,产品已经系列化。频率范围从0.5～40GHz,有点频、     

一种实用的锁相环路

锁相技术已在广播电视、通信、仪器、计算机等领域得到广泛应用,尤其集成锁相环路的出现,使销相电路在电子技术等方而的应用更加普及。锁相环是一个频率与相位的控制系统,其控制性能的优劣主要看“准”和“快”。准是指环路的锁定精度,即锁定后的剩余相差越小越好,以达到压控信号与标频信号的准确同步;快是指失锁到锁定的时间,亦称锁定时间,这时间越短越好。下面介绍一种锁相环路,该电路在中波同步广播激励器中使用,实现相位同步、锁定快、捕捉范围宽、稳定可靠。其原理框图如图l所示。1主要特点该销相环路的主要特点,一是以彩色…     

适用于空间分集的GNSS信号跟踪环路设计

为解决火箭发射时姿态变化造成的信号接收不连续问题,提出了一种空间分集方式下的GNSS信号双锁相环路设计,对环路稳定性进行了分析,并给出了环路在单、双环切换时的处理方案.通过对此环路结构的分析和数学推导,证明了环路的可行性,并通过仿真对环路在各个状态下的稳定进行了验证.仿真结果表明,双锁相环路在各个状态下均能实现稳定跟踪...     

频谱分析仪中小数环的一点改进

本文介绍了在AV4033频谱分析仪中小数环的的原理及各部分的功能。为了解决环路工作过程中不稳定,容易失锁的问题,在环路滤波器前端电阻上并联一个补偿电容,并提供了获取电容值的算法。采用该方法后,明显提高了小数环路的增益,促进了环路的捕捉与锁定。     

基于YIG振荡器的宽带频率综合器设计

针对提出的频率综合器性能指标要求,对基于钇铁石榴石(YIG)振荡器的C波段频率综合器的设计方案进行了简要介绍。采用混频环的方式并选用低相噪的YIG振荡器,降低了分频比和相位噪声。建立了混频环的相位噪声模型,对相位噪声进行了分析和估算。介绍了关键器件YIG振荡器和辅助环锁相芯片HMC698LP5的应用,给出了实验测试结果并进行了分析。该设计已在工程实际中得到了应用和验证,对于其他频段的高性能频率综合器设计有一定借鉴作用。     

Phase modulation of a loop phase-locked grid oscillator array

In this letter, we describe a method for phase modulation of a loop phase-locked grid oscillator array and report results obtained in a test bed implementation of the method. The key to the scheme lies in introducing the phase-locked loop (PLL) in such a way that the modulating data stream is introduced in parallel with the loop rather than through it, thereby circumventing the bandwidth limitation of the PLL. The experiment was performed at 4.7 GHz with a phase-locked grid oscillator array. The grid oscillator was successfully modulated by a 1 MHz signal, which is ten times higher than the bandwidth of the phase-locked loop     

Phaselock system for millimeter-wave Gunn oscillators used in radio astronomy and laboratory spectroscopy

A frequency-agile heterodyne phaselock loop (PLL) system for millimeter-wave Gunn-effect oscillators between 40 and 110 GHz is described. The Gunn oscillators are phase-locked via the bias in an active second-order servo loop. A facility for fast frequency switching with a maximum rate of 10 kHz and a frequency separation up to 80 MHz is provided. Measurements on the spectral characteristics of a phase-locked Gunn oscillator are presented. The described PLL system is used in radio astronomy and laboratory molecular spectroscopy.     

Charge pump boosting technique for power noise immune high-speedPLL implementation

A phase-locked loop (PLL) with a charge pump boosting technique is described. The technique enables the voltage controlled oscillator circuit in the PLL to run faster than conventional circuits at low supply voltage. This design method is applicable to PLLs with low jitter, high-speed characteristics in environments with high supply noise     

A 1.8~3.2-GHz fully differential GaAs MESFET PLL

A 1.8~3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74~3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8~3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz     

Analysis of oscillators with external feedback loop for improvedlocking range and noise reduction

A simple scheme for enhancing the locking/capture range and phase-noise performance of FET-based voltage-controlled oscillators (VCO's) is presented using a low-pass feedback loop from the oscillator output to the varactor tuning port. The nonlinearity of the FET provides for mixer or phase detector behavior (a self-oscillating mixer). The resulting feedback oscillator advantageously combines the principles of a conventional injection-locked oscillator (ILO) and phase-locked loop (PLL), which we refer to as an injection-locked phase-locked loop (ILPLL). The analysis suggests that the ILPLL can be designed for superior near-carrier phase-noise performance compared with conventional ILO or PLL circuits. A 10-GHz prototype was fabricated, which demonstrated a locking range more than double that of the isolated VCO injection-locking range over the same range of injected signal power     

YIG微波锁相环的非线性性能分析

钇铁石榴石(YIG)振荡器具有调谐范围宽、调谐线性好、噪声低等优点,在部分覆盖式微波频率综合实验中,用它作压控振荡器(VCO),在 24 GHz 频段内,成功地综合出上万个具有高稳石英晶振稳定度和准确度的微波频率。本文从理论上研究了磁场滞后效应对此实验中的YIG锁相环非线性性能的影响。用解析近似法推导出存在磁场滞后效应的YIG锁相环的三个公式,即平均频差公式、捕捉时间公式和捕捉带公式,公式具有明确的物理意义。实验表明,捕捉带公式与实际测量结果有较好的一致性。     

Fully integrated CMOS phase-locked loop with 15 to 240 MHz lockingrange and ±50 ps jitter

A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

以DDS为参考的PLL在现代电台设计中的应用

介绍了DDS(直接数字频率合成)技术及PLL(锁相环)频率合成技术的工作原理及特点,给出了现代电台设计中基于DDS的频率合成器的设计方案.采用DDS输出作为参考的PLL频率合成器非常适合用做现代电台的本振.