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1.
The failure of dc/dc converters can directly result in electronic systems working unconventionally or significant downtime. To pre-determine time to failure and generate substantial safety and cost benefits, it is necessary to assess the extent of deviation of dc/dc converters from its expected state of health in real time and predict time to failure in advance. This paper presents a novel prognostic method for predicting the time to failure of dc/dc converters. The process involves identifying precursor parameters, determining prognostic of failure, and determining a criterion for predicting time to failure. The output voltage is used as a precursor parameter and directly monitored when the converter with a given load periodically operates at different temperature stresses. The phenomenon that the differences of output voltages collected at different temperature stresses begin to increase with a large (or small) fluctuation is detected in collected output voltages. This phenomenon is identified as a prognostic of failure. A percentage of the initial difference is used as the criterion for predicting time to failure. A case study is given to illustrate the procedure that how to monitor output voltages, detect prognostic and predict time to failure. The results show the health state could be assessed in real time and the time to failure could be predicted in advance. Furthermore, the deviation of the predicted time to failure from the actual time to failure could meet the demand of a considered acceptable range in engineering practice.  相似文献   

2.
要从单个正极性输入产生双极性(正和负)输出的常见方法是采用变压器.虽然这种设计比较简单,但变压器本身会带来体积问题.把一个变压器装入一台要求减小电路占用面积和高度的设备中,这是具有挑战性的.图1所示电路可以从由3V~10V输入产生±5V输出,适用于没有地方安装变压器的设备.该电路所用的一种结构,能在DC/DC变换器处于关机模式时切断两个输出,这样就使处于关机(待机)模式时的静态电流很小.  相似文献   

3.
使用JFET的自偏置特性可以建立一个DC/DC转换器,它能用太阳能电池、热电偶和单级燃料电池等电源工作,这些电源电压都低于600 mV,有的甚至低至300 mV。  相似文献   

4.
DC/DC转换器制造商C&DTechnologies公司(位于美国亚利桑那州图森)开发的PositionPerfect引脚技术消除了元件在组装时发生移动的可能性,从而使无引线SMTDC/DC转换器的机械安装整体性和精确性均有所提高。与传统技术相比,此项技术还能够使转换器引脚提供更高的电流,从而确保将满载的额定电流输送至主PC电路板上。该技术运用了SMT互连,这种SMT互连采用了由高速自动模锻工艺固定在转换器上的独特铜柱。在模锻处理之后进行的修剪形成了极端平整的表面,从而确保了引脚的共面误差小于0.004英寸,并且消除了元件的移动。将引脚固定在转换器…  相似文献   

5.
Ajoy Raman 《电子设计技术》2007,14(11):124-124,128
本设计实例能以最少的元件数实现利用单变压器推挽DC/DC转换器的固有倍压特性的宽范围倍压器.它采用高压达林顿晶体管阵列驱动器ULN2023A来实施.该电路具有5V~30V的较宽输入电压范围,并能以适宜的效率提供了1W~4W的典型电源输出.  相似文献   

6.
An analysis and design of single-stage, single-switch bi-flyback ac/dc converter is presented. The main flyback stage controls the output power from the link capacitor voltage with Discontinuous Conduction Mode (DCM) or Continuous Conduction Mode (CCM) operation, while an auxiliary flyback stage supplies the power to the output directly from ac line input with DCM operation.

This scheme can effectively reduce the voltage stress on the link capacitor and can achieve the power factor correction (PFC) without a dead band at line zero-crossings, which reduces the harmonic distortion in ac line current. Theoretical analysis of the converter is presented and design guidelines to select circuit components are given. The experimental results on a 60?W (15?V, 4?A), 100?kHz ac/dc converter show that maximum link voltage and maximum efficiency are around 415?V and 82%, respectively. The power factor is above 0.96 under universal line input and load conditions.  相似文献   

7.
Single-stage line-coupled ac/dc converter with high power factor and ripple-free input current is proposed. The proposed power factor correction circuit can achieve high power factor and ripple-free input current using a coupled inductor. Experimental results for a 400?W converter at a constant switching frequency of 100?kHz are obtained to show the performance of the proposed converter.  相似文献   

8.
Andover  新宇 《今日电子》2001,(8):28-28
零电流开关器件产生的谐波和寄生噪声较少,适合于噪声敏感型用途  相似文献   

9.
最近推出的各种集成式降压DC/DC变换器均已采取对外接低侧MOSFET同步整流器的电压降采样的方法,无需高侧电流检测电阻器。这种拓扑节省了检测电阻器的成本和印制电路板的空间,也适当提高了电路效率。但是,MOSFET的导通电阻与温度有很大的相关性,它决定了限流大  相似文献   

10.
The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 μm CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted  相似文献   

11.
A new single-stage power factor corrected ac–dc converter for universal line applications is proposed in this paper. This converter has a buck topology as a power factor corrector. The dc bus voltage of the proposed converter is always lower than the peak input voltage at any load condition. Therefore, the problem of high dc bus voltage under the light load condition for the single-stage converter is solved, especially in the case of universal line applications. The design equations are presented for the proposed converter and a design example for a 5V 12A application is presented. The theoretical analysis and experimental results show that the dc bus voltage can be limited within 260V and the line input current harmonics can meet IEC 61000-3-2 Class D requirements at any load conditions for the line input voltages from 90 to 260Vac.  相似文献   

12.
A dc transformer     
Giaever  I. 《Spectrum, IEEE》1966,3(9):117-122
Although conventional transformers are ac, a device that may be termed a dc transformer has been constructed by using superconductors. To provide an understanding of how such a transformer would operate, some of the properties of type I and type II superconductors are reviewed. Since the dc transformer under discussion is constructed from thin superconducting films, the main emphasis is on these structures; the concept of flux motion is also explained. The result of the work described is a device in which a direct current or voltage can be transformed, and in which it is possible to extract power from the secondary circuit.  相似文献   

13.
The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.  相似文献   

14.
The design and fabrication of a superconducting A/D converter using Josephson technology are described. The 4-b A/D converter circuit was fabricated using a ten-level all-Nb technology. It uses a self-aligned lift-off process to define the Nb-Al2O3 -Nb Josephson junctions. Results from experiments performed on the prototype system at a few kilohertz sampling rate are presented  相似文献   

15.
This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators  相似文献   

16.
The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.  相似文献   

17.
《今日电子》2001,(2):31-34
代码转换器提高DSP效率 TLV320AIC10 16位代码转换器提供连续数据传输,可支持DSP自动缓冲单元,减少因缓冲(最高达64kB)不足而引起的中断。该器件特性有每秒22k的采样速率,一个串行接口,增益范围为-36~24dB的可编程增益放大器,一个2:1模拟多路复用器,以及节能备用模式。其它性能包括:工作电压3~5.5V,在采样速率为每秒8k时功耗为39mW。  相似文献   

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20.
数模转换器(D/A)在许多应用中起着重要的作用.了解常用D/A架构及相关的权衡折衷方法,将有助于您针对某项具体应用选择最为合适的D/A.  相似文献   

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