HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide

The authors have fabricated low-temperature fully silicided YbSi/sub 2-x/-gated n-MOSFETs that used an HfAlON gate dielectric with a 1.7-nm EOT. After a 600 /spl deg/C rapid thermal annealing, these devices displayed an effective work function of 4.1 eV and a peak electron mobility of 180 cm/sup 2//V/spl middot/s. They have additional merit of a process compatible with current very large scale integration fabrication lines.     

Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO/sub 2/ gate dielectric and TaN gate electrode

Schottky source/drain (S/D) transistors using Pt-germanide and HfO/sub 2//TaN gate stack are fabricated on Ge-substrate with conventional self-aligned top-gate process. It was found that Pt-germanide provides promising properties for p-MOSFET: negative effective hole barrier height, low resistivity, atomically sharp junction with Ge with good morphology. Pt-germanide Ge-p-MOSFETs showed well-behaved I/sub D/-V/sub D/ characteristics and much suppressed I/sub off/ compared to Ni-germanide and conventional heavily doped S/D MOSFETs.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High- $k$ MISFETs

We have proposed a (111)-faceted metal source and drain (S/D) with a metal gate and a high-k gate dielectric for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The metal S/D is formed by epitaxially grown nickel disilicide. N-type or p-type dopants are segregated in the atomically flat metal/Si interfaces that help to reduce the effective Schottky barrier height between the epitaxial metal and silicon. Therefore, a single type of metal S/D can work for both n-type and p-type MISFETs. The dopant segregation is realized by an ion implantation into the epitaxial silicides and a subsequent low-temperature annealing. Operations of 6-nm-long n-type and p-type silicon-on-insulator MISFETs that came with a fully silicided gate electrode and a high-k gate dielectric were experimentally demonstrated. The excellent short-channel effect immunity due to the trapezoidal channel was also verified by numerical simulation.     

Structural optimization of SUTBDG devices for low-power applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.     

High work function Ir/sub x/Si gates on HfAlON p-MOSFETs

We have fabricated the fully silicided Ir/sub x/Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950/spl deg/C rapid thermal annealing, the fully Ir/sub x/Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm/sup 2//V/spl middot/s, and the advantage of being process compatible to the current VLSI fabrication line.     

MESFET fabrication on MOCVD grown Hg/sub 1-x/Cd/sub x/Te

The fabrication of the first MESFET structures on Hg/sub 1-x/Cd/sub x/Te is reported using MOCVD grown layers on GaAs substrates. The 6 mu m gate devices exhibited a room temperature transconductance of 1.0 mS/mm and pinch off voltage of -4.0 V. The Schottky barrier characteristics of the devices were critically dependent on the stoichiometric x ratio of the Hg/sub 1-x/Cd/sub x/Te with diode formation evident only at x >0.5.<>     

A new Pd-InP Schottky hydrogen sensor fabricated by electrophoretic deposition with Pd nanoparticles

In this letter, a new Pd-InP Schottky diode hydrogen sensor fabricated by electrophoretic deposition (EPD) combined with nanosized Pd particles is first proposed and demonstrated. Experimentally, the studied device exhibited excellent current-voltage rectifying characteristics with a large Schottky barrier height (SBH) of 829 meV. At 303 K, a high saturation sensitivity ratio of 38 was found under a very low hydrogen concentration of 15 ppm H/sub 2//air. As raising the hydrogen concentration to 1.0% H/sub 2//air, the SBH lowering of the studied devic"dq"e reached to 307 meV and the sensitivity ratio was high as 1.29/spl times/10/sup 5/ with a very rapid response, which far prevailed over those fabricated by the conventional thermal evaporation and electroless plating techniques. Consequentially, the EPD Pd-InP Schottky diode with extremely effective Pd gate is promising for the fabrication of high-performance hydrogen sensors.     

Fully silicided NiSi and germanided NiGe dual gates on SiO/sub 2/ n- and p-MOSFETs

We have fabricated the fully silicided NiSi and germanided NiGe dual gates n- and p-MOSFETs on 1.9 nm thick SiO/sub 2/ gate dielectric. The extracted work functions of fully NiSi and NiGe gates from thickness-dependent flat band voltage were 4.55 and 5.2 eV respectively, which may provide possible wide work function tuning using NiSi/sub t-x/Ge/sub x/. In additional to the lower gate current than Al gate n- and p-MOSFETs, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility values with special advantage of process compatible to current VLSI fabrication line.     

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

Dopant-free FUSI Pt/sub x/Si metal gate for high work function and reduced Fermi-level pinning

High work function (4.9 eV) on high-/spl kappa/ gate dielectric, which is suitable for bulk p-MOSFET, has been achieved using fully silicided (FUSI) Pt/sub x/Si gate without boron predoping of polysilicon. High concentration of Pt in FUSI Pt/sub x/Si using Ti capping layer on Pt in the FUSI process is a key to achieving high work function and reduced Fermi-level pinning on high-/spl kappa/ dielectric. By combining with substituted Al (SA) gate for nMOSFET, a wide range of work function difference (0.65 eV) between n and pMOSFETs is demonstrated, without any adverse effects of polysilicon predoping.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Improved hydrogen-sensitive properties of MISiC Schottky sensor with thin NO-grown oxynitride as gate insulator

Thin oxynitride grown in NO at low temperature was successfully used as gate insulator for fabricating MISiC Schottky hydrogen sensors. Response properties of the sensors were compared with other MISiC Schottky sensors with thicker or no oxynitride. It was found that the thin oxynitride played an important role in increasing device sensitivity and stability. Even at a low H/sub 2/ concentration, e.g., 100-ppm H/sub 2/ in N/sub 2/, a significant response was observed, indicating a promising application for detecting hydrogen leakage. Moreover, a rapid and stable dynamic response on the introduction and removal of H/sub 2//N/sub 2/ mixed gas was realized for the sensor. Improved interface properties and larger barrier height associated with the thin oxynitride are responsible for the excellent response characteristics. As a result, NO oxidation could be a superior process for preparing highly sensitive and highly reliable MISiC Schottky hydrogen sensors.     

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

Improved Schottky barrier on n-Sb/sub 2/S/sub 3/ films chemically deposited with silicotungstic acid (solar cells)

The first fabrication of low cost Schottky barrier solar cells on chemically deposited polycrystalline n-Sb/sub 2/S/sub 3/ thin films is reported. It is observed that in the films deposited with silicotungstic acid and annealed, the Schottky barrier height ( phi /sub b/) of the Au/n-Sb/sub 2/S/sub 3/ junctions is considerably improved from 0.54 to 0.76 eV. The ideality factor n decreased from 2.32 to 1.08 and the reverse-saturation current density J/sub 0/ from 3.2*10/sup -6/ to 1.5*10/sup -9/ A cm/sup -2/. Under AM1 illumination, the improved diode exhibited a conversion efficiency of approximately 3%.<>     

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.     

Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers

Dual-work-function metal gates fabricated by full silicidation (FUSI) of Co-Ni bi-layer with doped poly-Si were investigated for the first time, along with single-metal FUSI systems of CoSi/sub 2/ and NiSi. Complete conversion of poly-Si into Co-Ni alloy silicided metal gate (FUSI) Co/sub x/Ni/sub 1-x/Si/sub 2/ was demonstrated. Although a linear relationship between work function and Ni percentage was observed for FUSI of undoped poly-Si systems, the work functions of doped Co/sub x/Ni/sub 1-x/Si/sub 2/ are almost identical to those of doped NiSi FUSI metal gates. The alloy FUSI metal gates explored in this letter provide a new class of metal gates for CMOS devices that combine the advantages of both NiSi and CoSi/sub 2/, i.e., proper work function tunability of NiSi and high thermal stability of CoSi/sub 2/.     

High-field effects in silicon nitride passivated GaN MODFETs

This paper presents a detailed study of high-field effects in GaN MODFETs. Degradation of DC characteristics and change of flicker noise due to hot electron and high-reverse current stresses in Si/sub 3/N/sub 4/ passivated GaN MODFETs have been investigated. The authors observe that during hot electron stress, electron trapping in the barrier layer and interface state creation occur. These cause a positive shift of V/sub t/, reduce I/sub D/, skew the transfer characteristics, and degrade g/sub m/. Flicker noise (1/f) measurements show that after hot electron stress, the scaled drain current noise spectrum (S/sub I(D)//I/sub D//sup 2/) decreases in depletion, but increases only slightly in strong accumulation, corroborating the creation of interface states but only a small creation of transition-layer tunnel traps that contribute to 1/f noise. During high-reverse current stress, electron trapping dominates for the first 50-60 s and then hole trapping and trap creation begin to manifest. However, there still is net electron trapping under the gate after one hour of stress. The degradation processes bring about a positive shift of V/sub t/, degrade I/sub D/ and g/sub m/, and increase reverse leakage. After high-reverse current stress, S/sub I(D)//I/sub D//sup 2/ increases substantially in strong accumulation, indicating the creation of transition layer tunnel traps.