矢量空间秘密共享-多重签名方案

本文把矢量空间秘密共享方案与多重签名方案结合起来 ,提出了一种新的签名方案 ,即矢量空间秘密共享 -多重签名方案 ,并对该方案的安全性进行了分析 .在该方案中 ,任何参与者的授权子集能容易地产生群签名 ,而参与者的非授权子集不可能产生有效的群签名 ,验证者可通过验证方法验证个体签名和群签名的合法性 .该方案能保证一个参与者的授权子集的群签名不能被其他参与者子集所伪造 ,而且可以跟踪被怀疑的伪造者并将其曝光 .该方案能抵御各种可能的攻击 .     

矢量空间秘密共享—多重签名文字

本文把矢量空间秘密共享方案与多重签名方案结合起来，提出了一种新的签名方案，即矢量空间秘密共享-多重签名方案，并对该方案的安全性进行了分析。在该方案中，任何参与者的授权子集能容易地产生群签名，而参与者的非授权子集不可能产生有效的群签名，验证者可通过验证方法验证个体签名和群签名的合法性。该方案能保证一个参与者的授权子集的群签名不能被其他参与者子集所伪造，而且可以跟踪被怀疑的伪造者并将其曝光。该方案能抵御各种可能的攻击。     

矢量空间秘密共享群签名方案

本文通过引入矢量空间秘密共享技术和阈下通道技术,提出了一种新的群签名方案.在本签字体制建立后,可以加入或删除成员.一个部门只有在一定数量成员的参与下,才可以生成有效的群签名.接收者可以验证签名的有效性,但是不能判断出群签名出自哪一个部门.当有争端发生时,仲裁者可以"打开"群签名,确定签名的部门.此签字的公钥长度是独立的."打开"过程通过阈下通道实现.     

矢量空间RSA数字签名方案

基于矢量空间秘密共享方案和RSA签名方案提出了一种新的签名方案，即矢量空间RSA签名方案，该方案包括文献[1]中方案作为其特殊情况。在该方案中，N个参与者共享RSA签名方案的秘密密钥，能保证矢量空间访问结构I中参与者的授权子集产生有效的RSA群签名，而参与者的非授权子集不能产生有效的RSA群签名。     

门限多重秘密共享方案

本文提出了一个门限多重秘密共享方案,其安全性依赖于RSA数字签名的安全性,即大数分解的困难性.该方案具有如下特点:参与者的子秘密可反复使用,可用来共享任意多个秘密;能有效预防管理员欺诈及参与者之间的互相欺骗;此外,在验证是否有欺诈行为存在的过程中,不需要执行交互协议.     

基于离散对数有序多重签名

提出了一种基于离散对数型的有序多重签名方案，该方案无需增设第三方信任机构，减少了通信和计算工作量。同时他的安全性基于求解离散对数难题，因此是一种安全有效的有序多重签名方案。     

基于广义ElGamal型的多重盲签名方案

数字签名是人工手动签名的一种电子模拟，盲签名是一种特殊的数字签名技术，除了满足一般数字签名的3个基本特征（不可否认；不能伪造；能够仲裁）外，盲签名还必须满足2个附加的条件：签名者不知道所签文件或消息的具体内容及在签名被文件或消息的拥有者公布后签名者不能追踪签名。现在盲签名技术被广泛地应用在很多重要的实际工作中。本文分析了基于二元仿设变换的广义ElGamal型盲签名方案，并指出了文献[4]中一些错误结论。本文在上述盲签名方案的基础上构造了他们的多重盲签名方案，他使得多个签名人能够共同对盲化的消息实施签名。     

基于多项式秘密共享的前向安全门限签名方案

采用多项式秘密共享的方法,提出了一种新的前向安全的门限数字签名方案.该方案有如下特点:即使有多于门限数目的成员被收买,也不能伪造有关过去的签名;保持了公钥的固定性;在规则的时间间隔内更新密钥:可抵御动态中断敌手.假设因式分解是困难的,证明了该方案在随机预言模型中是前向安全的.     

一个高效的门限共享验证签名方案及其应用

基于离散对数问题提出一个新的门限共享验证签名方案，该方案是EIGamal签名方案和Shamir门限方案的结合。在该方案中，n个验证者中任意t个可以验证签名的有效性，而t-1个或更少的验证者不能验证签名的有效性。伪造该方案的签名等价于伪造EIGamal签名。与已有方案相比，该方案的签名效率更高。最后基于该门限共享验证签名方案提出一个新的口令共享认证方案。     

基于Nyberg-Rueppel 签名体制的盲代理多重签名方案

为了实现一个盲代理签名能够同时代表多个原始签名人签名,在对盲代理签名研究的基础上,首次提出了盲代理多重签名这一概念,该签名克服了一个盲代理签名只能代表一个原始签名人签名的局限性。此外,在Nyberg-Rueppel盲代理签名和代理多重签名2种体制研究的基础上,基于离散对数,分别提出了具有盲代理签名和代理多重签名双重性质的第一类盲代理多重签名方案和第二类盲代理多重签名方案,并对2方案的安全性进行了论证。     

A Shared Buffer Memory ATM Access Switch

１ＩｎｔｒｏｄｕｃｔｉｏｎＴｈｅＡｓｙｎｃｈｒｏｎｏｕｓＴｒａｎｓｆｅｒＭｏｄｅ（ＡＴＭ）ｉｓｃｏｎｓｉｄｅｒｅｄａｐｒｏｍｉｓｉｎｇｔｅｃｈｎｉｑｕｅｔｏｔｒａｎｓｆｅｒａｎｄｓｗｉｔｃｈｖａｒｉｏｕｓｋｉｎｄｓｏｆｍｅｄｉａ，ｓｕｃｈａｓｔｅｌｅ...     

共享存储器ATM交换机性能分析

本文提出一种分析共享缓冲器ＡＴＭ交换机性能的新方法，该方法为复杂的排队问题的求解提供了新的途径。该方法是采用Ｍａｒｋｏｖ链一步转移概率矩阵求得信元队长稳态概率分布的精确算法，计算机模拟结果验证了该方法的有效性和正确性。     

模块化结构的ATM交换节点的性能分析

模块化结构是形成大容量ＡＴＭ交换节点的最有效手段，本文提出一种分析模块化结构的ＡＴＭ交换节点性能的新方法，该方法通过引入虚队列考虑了相邻模块间的相关性，与计算机模拟相比，分析结果在整个负载变化范围内都有很高的准确性，方法适用于任意大小模块并采用输出排队和以Ｂａｎｙａｎ网为互连网的ＡＴＭ交换节点的性能分析。     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

ATM中突发业务的缓存性能分析

主要讨论突发业务情况下的ATM缓存的排队性能.首先采用状态转移概率进行模型分析,然后再给出信元丢失率和信元延时的分布.     

一种ATM交换结构性能分析方法

本文给出了ＡＴＭ交换结构性能分析的有效数学方法，通过分析几种业务流情况下不同缓冲方式ＡＴＭ交换结构的信元丢失率和时延特性，证明了该方法的正确性和有效性。     

PERFORMANCE EVALUATION OF NON-BLOCKING ATM SWITCHES UNDER VARIOUS TRAFFIC AND BUFFERING SCHEMES

Broadband integrated services digital networks (BISDN) are designed to offer a variety of services with bit rates ranging from several kb/s (e.g. teleactions) to hundreds of Mb/s (e.g. HDTV), and in some cases approaching Gb/s (e.g. in interconnections of high-speed LANs). A multiplicity of rates and the burstiness of traffic sources lead naturally to systems based on the fast packet switching (or asynchronous transfer mode) concept. The requirements of data buffering and high-speed processing of packet headers have resulted in a plethora of proposals for ATM switching nodes and an equal number of ways for evaluating them. In particular, the class of non-blocking architectures of ATM switches has received the most attention from the research community. This paper reviews this class of architecture with emphasis on contention resolution methods and communication traffic performance. The contention resolution methods are divided into four categories: input buffering, output buffering, shared buffering, and hybrid buffering. The communication traffic characteristics are divided into two categories: uniform traffic and bursty traffic.     

Shared buffer ATM switch with doubly linked lists

The Shared buffer memory switch (SBMS) architecture was originally proposed as an effective approach to implement ATM switch fabrics. However, in this paper we find that if an error occurs in the address chain memory of one linked list which stores the address of the next cell in the shared buffer memory, the erroneous situation will spread over all linked lists in the SBMS in a short time. In order to prevent the fault spread phenomenon, we propose two doubly linked list based architectures to combat address chain failure; these are referred to as the Flush and In-Seq schemes. The first scheme flushes the remaining cells in the faulty queue but collect their addresses for later usage. The second scheme outputs the remaining cells in their correct sequence. From our simulation, if the error injection rate is low, the performance of the In-Seq scheme experiences slight degradation compared with the errorfree situation.     

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Grouping output channels in a shared‐buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared‐buffer channel‐grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real‐life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented. Copyright © 2005 John Wiley & Sons, Ltd.     

ATM基本交换单元的研究与实现

文章提出并实现了一种共享缓存式ＡＴＭ基本交换单元的设计方案,该交换单元有６条输入输出线路,它由１０片大容量ＦＰＧＡ组成。通过简单的电路修改,用两片超大容量ＦＰＧＡ可以实现９×９或１８×１８共享缓存的ＡＴＭ基本交换单元。