An embedded 32-b microprocessor core for low-power andhigh-performance applications

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-μm CMOS process implementing the ARM^TM V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture^TM. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm² in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range     

DCG: deterministic clock-gating for low-power microprocessor design

With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined stages of a modern processor, the circuit block usage in the near future is known a few cycles ahead of time. Our experiments show an average of 19.9% reduction in processor power with virtually no performance loss for an eight-issue, out-of-order superscalar by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.     

一种低功耗,高性能微处理器复位芯片的设计

针对广泛使用电池供电的系统,由于电源电压监控的要求,系统复位电路的可靠性对整个系统的稳定性起着非常重要的作用,本文研究并设计一种低功耗,高性能的复位芯片,可以在系统上电,掉电的情况下向微处理器提供复位信号。当电源电压低于预设的门槛电压时,输出复位信号并在电源电压恢复到门槛电压以上继续持续复位一段时间,实现整个系统的平稳恢复,复位信号低电平有效。该芯片采用CMSC035标准CMOS工艺实现,采用Cadence Spectre仿真,工作电流仅为10μA。该芯片已成功应用于工业类控制系统中。     

Instruction cache organisation for embedded low-power processors

A low-power I-cache architecture is proposed that is appropriate for embedded low-power processors. Unlike existing schemes, the proposed organisation places an extra small cache in parallel alongside the L1 cache. Since it allows simultaneous accesses to both caches, the proposed scheme introduces little performance degradation. Using simple hardware logic (for sequential accesses) and a compiler transformation (for loop accesses), most L1 cache requests are served by a small cache, so that the amount of energy consumed by the L1 cache is significantly reduced. Experimental results show that for the SPEC95 benchmarks, the proposed organisation reduces the energy-delay product on average by 67.2% over a conventional cache design and 16.8% over the filter cache design     

近阈值低功耗8位微处理器的设计与实现

随着RFID、可穿戴设备和物联网等应用的兴起,低吞吐率、功耗和能耗敏感的芯片设计开始受到广泛的关注,基于阈值电压的低功耗电路设计成为新的发展方向。文中基于SMIC0.13μm1P6M混合信号工艺,通过设计面向近阈值电压的标准逻辑库,在采用标准Top-Down设计流程的基础上,完成了一款近阈值低功耗8位微处理器的设计。封装后芯片的测试结果表明,该微处理器的最低工作电压可达0.2V,工作频率1k Hz~25MHz。与基于传统逻辑库的微处理器比,在20MHz的工作频率下,功耗降低了36%。     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

Wordline voltage generating system for low-power low-voltage flashmemories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-μm flash memory process and achieved with very low stand-by current of 2 μA typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

嵌入式微处理器接口总线控制器的CPLD设计

介绍了用复杂可编制逻辑器件（CPLD）来实现嵌入式微处理器（MCU）和DSP处理器之间端口数据总线逻辑控制电路的设计,给出了接口数据总线逻辑的设计电路和部分仿真结果,证明本文采用的系统结构具有设计灵活、设计开发周期短的优点。     

新型的嵌入式LCD显示系统低功耗技术

随着多媒体在手持移动设备中的广泛应用，包含了显示缓存，显示控制模块，显示背光电路和显示屏的LCD（Liquid Crystal Display）显示系统在系统总功耗中占据了主要地位。提出了一种在文本浏览或使用编辑器时，降低显示系统功耗来达到减低总体功耗的系统设计，它利用新的动态色深调整，缓存驻留，关闭主存的方法使得总体功耗降低了20％～30％。     

Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.     

嵌入式微处理器的高层总线缓冲模型

本文针对嵌入式微处理器结构特征,提出了一种高层总线缓冲模型.随后根据提出的缓冲模型设计仿真算法,并根据实际的设备行为进行抽样统计分析,实现了带有缓冲设备的高层动态仿真.结果显示高层的仿真结果反映了实测电路级仿真的数据趋势,具有很好的一致性,证明了高层模型及仿真的有效性.     

SIGFRED: a low-power DTMF and signaling frequency detector

A CMOS circuit is presented containing an analog switched-capacitor processor for detection of dual-tone multifrequency, (DTMF) and signaling tones on a telephone subscriber line and a digital detection algorithm for postprocessing. The major issues for the design were that it should be compatible with a CMOS fabrication process for microcontrollers to be included as an on-chip component and that its power consumption should be as low as possible. It has been designed to work with a current of less than 0.5 mA at low supply voltages (2.5-3 V). The maximum supply voltage is limited to 6 V by the process     

Low-voltage,low-power Vt independent voltage reference for bio-implants

Biomedical electronics trends focus mainly on portability, miniaturization, connectivity, humanization, security and reliability. In this scenario, digital, low-cost CMOS technology plays a key role, especially in implementing complex systems into small devices with no batteries that can even be implanted in humans. Due to patient safety, the implanted devices are faced with challenges: device operation temperature and the RF power link must be kept extremely low.By using proper topologies, the whole system can be designed to operate in low-voltage and low-power modes to maintain low temperature and avoid tissue thermal hazards. In this paper, a voltage reference is proposed which can operate at as low as 500 mV with power consumption less than 100 nW. Furthermore, the proposed topology, based on composite transistors operating in weak inversion, shows a good rejection to threshold voltage V_t, which is an inherent CMOS dispersion parameter. Simulation results using the process corners show that the V_t dependence can be reduced to less than ±2% (3σ) at the body temperature and the PSRR can be as large as 65 dB for higher frequencies. One of the key features of the circuit is its simple design.     

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.